Related Documentation
- M, MX, T Series
- Egress Rewrite on SONET/SDH OC48/STM16 IQE PICs
- Scheduling and Shaping on SONET/SDH OC48/STM16 IQE PICs
- MDRR on SONET/SDH OC48/STM16 IQE PICs
- WRED on SONET/SDH OC48/STM16 IQE PICs
- Excess Bandwidth Sharing on SONET/SDH OC48/STM16 IQE PICs
- Packet Classification on SONET/SDH OC48/STM16 IQE PICs
- Translation Table on SONET/SDH OC48/STM16 IQE PICs
CoS on SONET/SDH OC48/STM16 IQE PIC Overview
The SONET/SDH OC48/STM16 IQE PIC is a clear-channel PIC that is designed to provide better scaling and improved queuing, buffering, and traffic shaping along with clear-channel functionality. Class of service (CoS) on the SONET/SDH OC48/STM16 IQE PIC supports per data-link connection identifier (DLCI) queuing at egress. The SONET/SDH OC48/STM16 IQE PIC can be used in Juniper Networks M320, MX240, MX960, T640, and T1600 routers.
The SONET/SDH OC48/STM16 IQE PIC supports the following CoS features:
- Eight queues per logical interface.
Note: Queue configuration in other modes, such as 4 queues per scheduler, is not supported on the SONET/SDH OC48/STM16 IQE PIC.
- Two shaping rates: a committed information rate (CIR) and peak information rate (PIR) per data-link connection identifier (DLCI).
- Sharing of excess bandwidth among logical interfaces.
- Five levels of priorities—three priorities for traffic below the guaranteed rate and two priorities for traffic above the guaranteed rate. By default, a strict-high queue gets the excess high priority and all other queues get the excess low priority.
- Ingress behavior aggregate (BA) classification.
- Translation table and egress rewrite.
- Egress delay buffer of 214ms.
- Forwarding class to queue remapping per DLCI.
- Weighted round-robin (WRR), weighted random early detection (WRED).
- Rate limit on all queues to limit the transmission rate.
- Per unit scheduling via DLCI at egress, where each DLCI
gets a dedicated set of queues and a scheduler. When per unit scheduling
is configured, the shaping can be configured at the logical and physical
interface levels.
Note: Because the SONET/SDH OC48/STM16 IQE PIC is not an oversubscribed PIC, there is no ingress queuing. Therefore, ingress scheduling or shaping is not supported in SONET/SDH OC48/STM16 IQE PIC.
- Packet or byte statistics are separately collected for
ingress and egress queues. The SONET/SDH OC48/STM16 IQE PIC provides
the following statistics:
- Ingress statistics:
- Per logical interface transmit and drop bytes/packets statistics (based on Layer 3).
- Per physical interface traffic bytes/packets statistics (based on Layer 2).
- Egress statistics:
- Per queue transmit and drop bytes/packets statistics (based on Layer 2).
- Per queue per color drop bytes/packets statistics (based on Layer 2).
- Per logical interface transmit and drop bytes/packets statistics (based on Layer 3).
- Per physical interface traffic bytes/packets statistics (based on Layer 2).
- Ingress statistics:
To configure the features mentioned above, include the corresponding class-of-service (CoS) statements at the [edit class-of-service] hierarchy level. The CoS configuration statements supported on the SONET/SDH OC48/STM16 IQE PIC are the same as the CoS configuration statements supported on the IQ2E PIC except for the following unsupported statements.
Unsupported configuration statements at the [edit chassis] hierarchy level:
- max-queues-per-interface
- no-concatenate
- q-pic-large-buffer
- red-buffer-occupancy
- ingress-shaping-overhead
- traffic manager mode
Unsupported configuration statements at the [edit class-of-service] hierarchy level:
- input-excess-bandwidth-share
- input-traffic-control-profile
- per-session-scheduler
- simple-filter
Related Documentation
- M, MX, T Series
- Egress Rewrite on SONET/SDH OC48/STM16 IQE PICs
- Scheduling and Shaping on SONET/SDH OC48/STM16 IQE PICs
- MDRR on SONET/SDH OC48/STM16 IQE PICs
- WRED on SONET/SDH OC48/STM16 IQE PICs
- Excess Bandwidth Sharing on SONET/SDH OC48/STM16 IQE PICs
- Packet Classification on SONET/SDH OC48/STM16 IQE PICs
- Translation Table on SONET/SDH OC48/STM16 IQE PICs
Published: 2013-07-31
Related Documentation
- M, MX, T Series
- Egress Rewrite on SONET/SDH OC48/STM16 IQE PICs
- Scheduling and Shaping on SONET/SDH OC48/STM16 IQE PICs
- MDRR on SONET/SDH OC48/STM16 IQE PICs
- WRED on SONET/SDH OC48/STM16 IQE PICs
- Excess Bandwidth Sharing on SONET/SDH OC48/STM16 IQE PICs
- Packet Classification on SONET/SDH OC48/STM16 IQE PICs
- Translation Table on SONET/SDH OC48/STM16 IQE PICs