Supported Platforms
Related Documentation
- ACX, MX Series
- Configuring the OAM F4 Cell Flows
- M, MX, T Series
- Enabling Passive Monitoring on ATM Interfaces
- Configuring the Maximum Number of ATM1 VCs on a VP
- Configuring a Point-to-Point ATM1 or ATM2 IQ Connection
- Configuring E3 and T3 Parameters on ATM Interfaces
- M, T Series
- Removing MPLS Labels from Incoming Packets
- Configuring ATM2 IQ VC Tunnel CoS Components
- MX Series
- ATM1 Physical and Logical Configuration Statement Hierarchies
- ATM2 IQ Physical and Logical Configuration Statement Hierarchies
- Supported Features on ATM1 and ATM2 IQ Interfaces
- Configuring Communication with Directly Attached ATM Switches and Routers
- Enabling ILMI for Cell Relay
- Configuring the ATM PIC Type
- Configuring ATM Cell-Relay Promiscuous Mode
- Configuring Layer 2 Circuit Transport Mode
- Configuring Layer 2 Circuit Cell-Relay Promiscuous Mode
- Configuring Layer 2 Circuit Trunk Mode Scheduling
- Configuring CoS Queues in Layer 2 Circuit Trunk Mode
- Configuring the Layer 2 Circuit Cell-Relay Cell Maximum
- Defining Virtual Path Tunnels
- Configuring a Point-to-Multipoint ATM1 or ATM2 IQ Connection
- Configuring a Multicast-Capable ATM1 or ATM2 IQ Connection
- Configuring Inverse ATM1 or ATM2 ARP
- Defining the ATM Traffic-Shaping Profile
- Configuring the ATM1 Queue Length
- Configuring the ATM2 IQ EPD Threshold
- Configuring Two EPD Thresholds per Queue
- Configuring the ATM2 IQ Transmission Weight
- Defining the ATM OAM F5 Loopback Cell Period
- Configuring the ATM OAM F5 Loopback Cell Threshold
- Configuring ATM Interface Encapsulation
- Configuring an ATM1 Cell-Relay Circuit
- Configuring PPP over ATM2 Encapsulation
- Configuring SONET/SDH Parameters on ATM Interfaces
- Example: Configuring ATM1 Interfaces
- Example: Configuring ATM2 IQ Interfaces
ATM Interfaces Overview
Asynchronous Transfer Mode (ATM) is a network protocol designed to facilitate the simultaneous handling of various types of traffic streams (voice, data, and video) at very high speeds over the same physical connection. By always using 53-byte cells, ATM simplifies the design of hardware, enabling it to quickly determine the destination address of each cell. This allows simple switching of network traffic at much higher speeds than are easily accomplished using protocols with variable sizes of transfer units, such as Frame Relay and Transmission Control Protocol/Internet Protocol (TCP/IP).
Although ATM was designed to operate without the requirement of any other networking protocol, other protocols are frequently segmented and encapsulated across multiple, smaller ATM cells. This makes ATM a transport mechanism for preexisting technologies such as Frame Relay and the TCP/IP family of protocols.
ATM relies on the concepts of virtual paths and virtual circuits. A virtual path, represented by a specific virtual path identifier (VPI), establishes a route between two devices in a network. Each VPI can contain multiple virtual circuits, each represented by a virtual circuit identifier (VCI).
VPIs and VCIs are local to the router, which means that only the two devices connected by the VCI or VPI need know the details of the connection. In a typical ATM network, user data might traverse multiple connections, using many different VPI and VCI connections. Each end device, just like each device in the network, needs to know only the VCI and VPI information for the path to the next device.
 | Note: The ATM three-bit payload type identifier (PTI) field is not supported. |
With ATM2 intelligent queuing (IQ) interfaces, you can configure virtual path (VP) shaping and Operation, Administration, and Management (OAM) F4 cell flows.
Related Documentation
- ACX, MX Series
- Configuring the OAM F4 Cell Flows
- M, MX, T Series
- Enabling Passive Monitoring on ATM Interfaces
- Configuring the Maximum Number of ATM1 VCs on a VP
- Configuring a Point-to-Point ATM1 or ATM2 IQ Connection
- Configuring E3 and T3 Parameters on ATM Interfaces
- M, T Series
- Removing MPLS Labels from Incoming Packets
- Configuring ATM2 IQ VC Tunnel CoS Components
- MX Series
- ATM1 Physical and Logical Configuration Statement Hierarchies
- ATM2 IQ Physical and Logical Configuration Statement Hierarchies
- Supported Features on ATM1 and ATM2 IQ Interfaces
- Configuring Communication with Directly Attached ATM Switches and Routers
- Enabling ILMI for Cell Relay
- Configuring the ATM PIC Type
- Configuring ATM Cell-Relay Promiscuous Mode
- Configuring Layer 2 Circuit Transport Mode
- Configuring Layer 2 Circuit Cell-Relay Promiscuous Mode
- Configuring Layer 2 Circuit Trunk Mode Scheduling
- Configuring CoS Queues in Layer 2 Circuit Trunk Mode
- Configuring the Layer 2 Circuit Cell-Relay Cell Maximum
- Defining Virtual Path Tunnels
- Configuring a Point-to-Multipoint ATM1 or ATM2 IQ Connection
- Configuring a Multicast-Capable ATM1 or ATM2 IQ Connection
- Configuring Inverse ATM1 or ATM2 ARP
- Defining the ATM Traffic-Shaping Profile
- Configuring the ATM1 Queue Length
- Configuring the ATM2 IQ EPD Threshold
- Configuring Two EPD Thresholds per Queue
- Configuring the ATM2 IQ Transmission Weight
- Defining the ATM OAM F5 Loopback Cell Period
- Configuring the ATM OAM F5 Loopback Cell Threshold
- Configuring ATM Interface Encapsulation
- Configuring an ATM1 Cell-Relay Circuit
- Configuring PPP over ATM2 Encapsulation
- Configuring SONET/SDH Parameters on ATM Interfaces
- Example: Configuring ATM1 Interfaces
- Example: Configuring ATM2 IQ Interfaces
Published: 2013-07-30
Supported Platforms
Related Documentation
- ACX, MX Series
- Configuring the OAM F4 Cell Flows
- M, MX, T Series
- Enabling Passive Monitoring on ATM Interfaces
- Configuring the Maximum Number of ATM1 VCs on a VP
- Configuring a Point-to-Point ATM1 or ATM2 IQ Connection
- Configuring E3 and T3 Parameters on ATM Interfaces
- M, T Series
- Removing MPLS Labels from Incoming Packets
- Configuring ATM2 IQ VC Tunnel CoS Components
- MX Series
- ATM1 Physical and Logical Configuration Statement Hierarchies
- ATM2 IQ Physical and Logical Configuration Statement Hierarchies
- Supported Features on ATM1 and ATM2 IQ Interfaces
- Configuring Communication with Directly Attached ATM Switches and Routers
- Enabling ILMI for Cell Relay
- Configuring the ATM PIC Type
- Configuring ATM Cell-Relay Promiscuous Mode
- Configuring Layer 2 Circuit Transport Mode
- Configuring Layer 2 Circuit Cell-Relay Promiscuous Mode
- Configuring Layer 2 Circuit Trunk Mode Scheduling
- Configuring CoS Queues in Layer 2 Circuit Trunk Mode
- Configuring the Layer 2 Circuit Cell-Relay Cell Maximum
- Defining Virtual Path Tunnels
- Configuring a Point-to-Multipoint ATM1 or ATM2 IQ Connection
- Configuring a Multicast-Capable ATM1 or ATM2 IQ Connection
- Configuring Inverse ATM1 or ATM2 ARP
- Defining the ATM Traffic-Shaping Profile
- Configuring the ATM1 Queue Length
- Configuring the ATM2 IQ EPD Threshold
- Configuring Two EPD Thresholds per Queue
- Configuring the ATM2 IQ Transmission Weight
- Defining the ATM OAM F5 Loopback Cell Period
- Configuring the ATM OAM F5 Loopback Cell Threshold
- Configuring ATM Interface Encapsulation
- Configuring an ATM1 Cell-Relay Circuit
- Configuring PPP over ATM2 Encapsulation
- Configuring SONET/SDH Parameters on ATM Interfaces
- Example: Configuring ATM1 Interfaces
- Example: Configuring ATM2 IQ Interfaces
