Channelized Interfaces Overview
Channelized interfaces enable you to configure a number of individual channels that subdivide the bandwidth of a larger interface and minimize the number of Physical Interface Cards (PICs) that an installation requires.
 | Note: Channelized intelligent queuing (IQ) and channelized enhanced intelligent queuing (IQE) interfaces require M Series Enhanced Flexible PIC Concentrators (FPCs) and MX Series Enhanced Flexible PIC Concentrators (FPCs). Wherever Junos configuration guides refer to channelized interfaces and PICs without the “intelligent queuing IQ or IQE” descriptor, they are referring to the original channelized interfaces and PICs. On M40e routers, all supported interface types support a maximum number of 784 traffic-bearing interfaces that can be created per interface port and includes ports on channelized PICs. MX Series routers support two Type 2 Channelized IQ PICs: OC12/STM4 IQE PIC with SFP and OC48/STM16 IQE PIC with SFP. Each channelized OC12/STM4 PIC supports 4 ports, and the channelized OC48/STM16 PIC supports one port. T640 and TX Matrix routers support Type 3 Channelized IQE PICs: 4xCOC12 IQE PIC with SFP. Channelized 4xCOC12 IQE PICs support deep-channelization of up to six OC slices (STS1) per port. For example, only six OC slices can be channelized to CT1/T1 or CE1/E1. Channelized COC48 IQE PICs support deep-channelization of up to six OC slices (STS1) in a block of 12 contiguous OC slices. For example, only six OC slices out of OC slice 1-12 can be channelized to CT1/T1 or CE1/E1. The PIC supports deep-channelization of maximum 24 OC slices in this way. Channelized OC48 IQE PICs do not support STS-48 clear-channel mode. IQ and IQE PICs do not support aggregated SONET (link bonding). For channelized IQ and IQE logical interfaces, you can configure class of service (CoS). For more information, see the Junos OS Class of Service Library for Routing Devices. |
