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Related Documentation
- ACX, M, MX, SRX, T Series
- clocking
- M, MX, T Series
- Configuring Channelized IQ and IQE SONET/SDH Loop Timing
- M, T Series
- Configuring the Channelized T3 Loop Timing
loop-timing
Syntax
(loop-timing | no-loop-timing);
Hierarchy Level
[edit interfaces ct3-fpc/pic/port t3-options],[edit interfaces e1-fpc/pic/port:0 sonet-options],[edit interfaces stm1-fpc/pic/port sonet-options]
Release Information
Statement introduced before Junos OS Release 7.4.
Description
For channelized IQ interfaces and non-IQ channelized STM1 interfaces only, configure the SONET/SDH or DS3-level clocking source.
 | Note: On M Series, MX Series, and T Series routers, under E1 channels, loop timing can be configured only at channel 0. When you configure on channel 0, it is applicable on all channels as internal by default. |
Options
loop-timing—Configure loop timing (external) clocking.
no-loop-timing—Configure line timing (internal) clocking.
Default: no-loop-timing
Required Privilege Level
interface—To view this statement in the configuration.
interface-control—To add this statement to the configuration.
Related Documentation
- ACX, M, MX, SRX, T Series
- clocking
- M, MX, T Series
- Configuring Channelized IQ and IQE SONET/SDH Loop Timing
- M, T Series
- Configuring the Channelized T3 Loop Timing
Published: 2013-08-01
Related Documentation
- ACX, M, MX, SRX, T Series
- clocking
- M, MX, T Series
- Configuring Channelized IQ and IQE SONET/SDH Loop Timing
- M, T Series
- Configuring the Channelized T3 Loop Timing
