Centralized Clocking Overview

Stratum 3 Clock Module

SCBE has a Stratum 3 centralized clock module that takes in synchronization sources on its reference input pins. When instructed by the clock selection algorithm, the clock module selects one of the reference inputs to lock its 19.44 MHz output clock. The MPCs select the chassis clock from the active SCBE to use it as a clock for their interface transmitters, thereby allowing the downstream routers to recover and synchronize to the chassis clock. A 20 MHz oscillator provides Stratum 3 free-run and holdover quality.

The clock module does not perform any automatic switching between the reference clocks, rather when Junos OS detects the loss of signal or clock, frequency inaccuracy, or phase irregularities, the clock module runs a clock selection algorithm and switches to the next highest-quality input reference.

The Stratum 3 clock modules—on the primary and the backup SCBE—are cross-wired to eliminate any phase transients during SCBE switchover. The backup SCBE locks to the primary’s Stratum 3 clock module.

BITS and GPS Support

Table 1 maps the Junos OS Release with the feature release of BITS and GPS on SCBE and SCBE2:

External Clock Interface Input

BITS and GPS can be configured on the external clock interface on the SCBE.

The following sections explain external clock interface input for BITS and GPS:

• External Clock Interface Input for BITS
• External Clock Interface Input for GPS

External Clock Interface Input for GPS

The GPS external clock interface supports:

• 1 MHz, 5 MHz, and 10 MHz frequencies.

• Pulse per second (PPS) signals on BNC connectors—a special cable converts signals between the BNC connector and the RJ–45 port. These signals are fed into the Stratum  3 centralized clock module for qualification and monitoring. After qualification, the GPS source becomes a valid chassis clock source candidate.

• Time of day (TOD) over a serial link. Most GPS source TOD string formats are supported by Junos OS, thereby enabling you to configure a generic TOD format string. This format tells the Routing Engine how to interpret the incoming TOD character string.

You must also configure an input SSM quality level value, where the quality level is used by the chassis clock selection algorithm when the quality level mode is enabled.

For the GPS receiver to be qualified as a clock source, the frequency and the PPS signal from it must be qualified by the SCBE Stratum 3 module. The SCBE is synchronized with the GPS source TOD.

The 10MHz frequency and PPS are supported by an RJ–45 connector for SCBE/SCBE2. Figure 1 illustrates the actual pinout of the connector.

Figure 1: RJ–45 Connector for SCBE/SCBE2

Table 2: RJ–45 Connector Pinout Information for SBE/SCBE2

Pin	Signal
1	RX
2	RX
3	1 PPS GND
4	TX
5	TX
6	10 MHz GND
7	1 PPS
8	10 MHz

Note:

Note that the GPS receiver is configured to support 10 MHz, 1 PPS, and TOD by default when it acts as a primary reference time clock.

Starting with 17.3R1, MX10003 router supports one GPS port per SPM which can be configured with 1MHz, 5MHz, and 10MHz frequencies and 1PPS signal.

Starting with 17.4R1, MX204 router supports GPS with 1MHz, 5MHz, and 10MHz frequencies and 1PPS signal.

External Clock Interface Output

The external clock interface can be configured to drive BITS or GPS timing output (GPS timing output for frequency and PPS signal only). The BITS or GPS output is configured to select the output clock source but in the absence of an output configuration, the BITS or the GPS output is disabled. When the external clock interface is configured for output, it selects the clock source on the basis of the configured source mode.

Starting with Junos OS Release 14.1, the external clock interface can be configured to drive BITS timing output. When the external clock interface is configured as a BITS timing output, the following scenarios occur:

• The external clock interface drives the BITS timing output.

  The chassis clock or the line clock are used as the source on the basis of the source mode configuration.

  The best—configured—line source is transmitted out the BITS interface, when the output source-mode statement is configured as line.

  The central clock module is set to holdover and the output is suppressed when the BITS output is configured and there are no valid clock sources available.

Redundancy

On SCBE, the primary and the secondary SCBs monitor their respective clock sources, and the external clock interface source is accessible only to its local clocking hardware. Therefore, the clock signals cannot be routed between the primary and the secondary SCB. Redundancy is achieved after a Routing Engine switchover. When a switchover occurs, the new primary SCB reruns the clock selection algorithm after the configured switchover time expires to select a new clock source.

Starting with Junos OS Release 14.1, on SCBE2, simultaneous BITS/BITS redundancy can be achieved because the external interfaces for BITS on the primary SCB and the secondary SCB are wired. Note that BITS redundancy is achieved without a Routing Engine switchover on SCBE2.

The following scenarios are supported for BITS/BITS redundancy:

• You can configure both the external interfaces for BITS input as reference clocks. Therefore, on the basis of the configured clock quality, one of the BITS inputs is considered as a primary clock source and the other as a secondary clock source.

• When the signal from the primary BITS input stops or degrades, the secondary BITS input takes over as primary, thereby providing redundancy across BITS interfaces.

GRES is supported on MX240, MX480, and MX960 routers with SCBE2.