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Centralized Clocking

Centralized Clocking is an internal clock synchronization approach where clocks of system are synchronized with one of clock of system.

Centralized Clocking Overview

The Enhanced SCB SCBE and the Enhanced SCB SCBE2 on the MX240, MX480, and MX960 routers support a Stratum 3 clock module that functions as a centralized point within the chassis for clock monitoring, filtering, holdover, and selection.

The Stratum 3 clock module produces a 19.44 MHz clock that is locked to a chassis synchronization clock source that is configured with the highest quality. The chassis clock signals are transmitted through the backplane to all the MPCs. The MPCs route the clock signals to their MICs, where the clock signals are driven out on all line interfaces thereby allowing the timing information to be distributed to the downstream routers.

You can configure external and line input synchronization sources at the [edit chassis synchronization output] hierarchy level, at the [edit chassis synchronization source interfaces] hierarchy level, and at the [edit chassis synchronization interfaces] hierarchy level, that become candidates to be selected by the chassis’s clock selection algorithm. The clock selection algorithm selects the highest-quality candidate clock source, which is then used as the chassis’s synchronization source.

The external clock interface on SCBE allows the building-integrated timing supply (BITS) clock source or the clock signals received from the global positioning system (GPS) receiver to act as an input clock source to the centralized timing circuit, or allows the centralized timing signals to act as an output clock source to the BITS source or to the GPS receiver.

The centralized mode is applicable to mobile backhaul infrastructures and for network transition from traditional TDM to Ethernet network elements with the support of Synchronous Ethernet.

Points to Remember

The following are the points to remember about centralized clocking:

  • Before you begin configuring centralized clocking on an interface that uses Synchronous Ethernet, ensure that you have configured the interface as a chassis synchronization source to the router that provides a Synchronous Ethernet clock source.

  • Before you remove the SCBE from the router, you must delete the configuration under the [edit chassis synchronization] hierarchy. Similarly, before you remove the SCBE2 from the router, you must delete the configuration under the [edit chassis synchronization] hierarchy.

  • On SCBE2, the external-0/0 interface is located on SCB0 and the external-1/0 interface is located on SCB1.

    When you configure the external clock interface for input, the BITS or GPS clock source—the source depends on how you configure the interface—sends the synchronized input clock signals to the centralized timing circuit in the SCBE. When you configure the external clock interface for output, the centralized timing circuit sends out the synchronized clock signal—BITS or GPS—to be transmitted to the downstream routers.

    For more information about SCBE hardware, see SCBE2-MX Description and SCBE2-MX LEDs.

The following sections explain centralized clocking and its features in detail:

Note:

Hereafter, all features that are explained for SCBE are also applicable for SCBE2 unless otherwise specified.

Stratum 3 Clock Module

SCBE has a Stratum 3 centralized clock module that takes in synchronization sources on its reference input pins. When instructed by the clock selection algorithm, the clock module selects one of the reference inputs to lock its 19.44 MHz output clock. The MPCs select the chassis clock from the active SCBE to use it as a clock for their interface transmitters, thereby allowing the downstream routers to recover and synchronize to the chassis clock. A 20 MHz oscillator provides Stratum 3 free-run and holdover quality.

The clock module does not perform any automatic switching between the reference clocks, rather when Junos OS detects the loss of signal or clock, frequency inaccuracy, or phase irregularities, the clock module runs a clock selection algorithm and switches to the next highest-quality input reference.

The Stratum 3 clock modules—on the primary and the backup SCBE—are cross-wired to eliminate any phase transients during SCBE switchover. The backup SCBE locks to the primary’s Stratum 3 clock module.

BITS and GPS Support

Table 1 maps the Junos OS Release with the feature release of BITS and GPS on SCBE and SCBE2:

Table 1: BITS and GPS Support on SCBE and SCBE2

Feature

Switch Control Board

Junos OS Release

BITS

SCBE

12.3

GPS

SCBE

13.3

BITS

SCBE2

13.3

External Clock Interface Input

BITS and GPS can be configured on the external clock interface on the SCBE.

The following sections explain external clock interface input for BITS and GPS:

External Clock Interface Input for BITS

When the BITS clock is qualified by the Stratum 3 clock module, it becomes a candidate clock source to the clock selection algorithm. BITS can simultaneously support both input and output clocking.

The external clock interface for BITS can recover:

  • A framed 1.544 Mbps (T1) clock or a framed 2.048 Mbps (E1) clock. The T1/E1 framer supports sending and receiving of SSM quality levels through SA bits.

  • An unframed 2048 kHz (G.703 T12) clock. You must configure an input SSM quality level when the external clock interface is configured for a signal type that does not support SSM, such as an unframed 2048 kHz (T12) clock, or a T1 superframe (T1 SF) clock.

On T1/T12 interfaces that do not support SSM, you must configure the SSM quality levels. On E1 interfaces, the Sa bits receive and transmit the SSM quality level.

MX10003 and MX204 routers support T1/E1 framed and 2.048MHz unframed clock input.

External Clock Interface Input for GPS

The GPS external clock interface supports:

  • 1 MHz, 5 MHz, and 10 MHz frequencies.

  • Pulse per second (PPS) signals on BNC connectors—a special cable converts signals between the BNC connector and the RJ–45 port. These signals are fed into the Stratum  3 centralized clock module for qualification and monitoring. After qualification, the GPS source becomes a valid chassis clock source candidate.

  • Time of day (TOD) over a serial link. Most GPS source TOD string formats are supported by Junos OS, thereby enabling you to configure a generic TOD format string. This format tells the Routing Engine how to interpret the incoming TOD character string.

You must also configure an input SSM quality level value, where the quality level is used by the chassis clock selection algorithm when the quality level mode is enabled.

For the GPS receiver to be qualified as a clock source, the frequency and the PPS signal from it must be qualified by the SCBE Stratum 3 module. The SCBE is synchronized with the GPS source TOD.

The 10MHz frequency and PPS are supported by an RJ–45 connector for SCBE/SCBE2. Figure 1 illustrates the actual pinout of the connector.

Figure 1: RJ–45 Connector for SCBE/SCBE2 RJ–45 Connector for SCBE/SCBE2
Table 2: RJ–45 Connector Pinout Information for SBE/SCBE2

Pin

Signal

1

RX

2

RX

3

1 PPS GND

4

TX

5

TX

6

10 MHz GND

7

1 PPS

8

10 MHz

Note that the GPS receiver is configured to support 10 MHz, 1 PPS, and TOD by default when it acts as a primary reference time clock.

MX10003 router supports one GPS port per SPM which can be configured with 1MHz, 5MHz, and 10MHz frequencies and 1PPS signal.

MX204 router supports GPS with 1MHz, 5MHz, and 10MHz frequencies and 1PPS signal.

External Clock Interface Output

The external clock interface can be configured to drive BITS or GPS timing output (GPS timing output for frequency and PPS signal only). The BITS or GPS output is configured to select the output clock source but in the absence of an output configuration, the BITS or the GPS output is disabled. When the external clock interface is configured for output, it selects the clock source on the basis of the configured source mode.

The external clock interface can be configured to drive BITS timing output. When the external clock interface is configured as a BITS timing output, the following scenarios occur:

  • The external clock interface drives the BITS timing output.

    The chassis clock or the line clock are used as the source on the basis of the source mode configuration.

    The best—configured—line source is transmitted out the BITS interface, when the output source-mode statement is configured as line.

    The central clock module is set to holdover and the output is suppressed when the BITS output is configured and there are no valid clock sources available.

G.703 2.048MHz Signal Type for BITS Interfaces

The ITU-T Recommendation G.703, Physical/electrical characteristics of hierarchical digital interfaces, is a standard method for encoding clock and data signals into a single signal. This signal is then used to synchronize various data communications devices, such as switches, routers and multiplexers at a data rate of 2.048 MHz. Both directions of the G.703 signal must use the same signal type. To configure signal type parameters for a building-integrated timing supply (BITS) interface, include the following statements at the [edit chassis synchronization ] hierarchy level:

Redundancy

On SCBE, the primary and the secondary SCBs monitor their respective clock sources, and the external clock interface source is accessible only to its local clocking hardware. Therefore, the clock signals cannot be routed between the primary and the secondary SCB. Redundancy is achieved after a Routing Engine switchover. When a switchover occurs, the new primary SCB reruns the clock selection algorithm after the configured switchover time expires to select a new clock source.

On SCBE2, simultaneous BITS/BITS redundancy can be achieved because the external interfaces for BITS on the primary SCB and the secondary SCB are wired. Note that BITS redundancy is achieved without a Routing Engine switchover on SCBE2.

The following scenarios are supported for BITS/BITS redundancy:

  • You can configure both the external interfaces for BITS input as reference clocks. Therefore, on the basis of the configured clock quality, one of the BITS inputs is considered as a primary clock source and the other as a secondary clock source.

  • When the signal from the primary BITS input stops or degrades, the secondary BITS input takes over as primary, thereby providing redundancy across BITS interfaces.

GRES is supported on MX240, MX480, and MX960 routers with SCBE2.