Clock Synchronization

Distributed Clocking Mode

In the distributing clocking mode, the Switch Control Board (SCB) supports synchronizing the MX Series router’s chassis to an internal Stratum 3 free-run oscillator. The Synchronous Ethernet timing messages are sent through the chassis to support the network timing trails that are traceable to a high-quality timing source. The timing messages are carried through the network by the Ethernet switches that were traditionally handled by time-division multiplexing (TDM) equipment over SONET/SDH interfaces. The distributing clocking mode is handled through ESMC messages. The ESMC support is based on the ITU-G.8264 specification. The ESMC messages transmit the clock quality of the line timing signal in the form of the (Synchronous Status Message) SSM TLV that is carried in the ESMC packet.For more information, see Ethernet Synchronization Message Channel Overview.

The distributed clocking mode has the following limitations:

• There is no SCB centralized clock module to synchronize the entire chassis.

• The recovered line timing is driven out only by the line interface of the 16-port 10-Gigabit Ethernet MPC.

• The distributed mode does not support external clock interface timing.

Centralized clocking mode overcomes these limitations by distributing and driving timing out on all the chassis line interfaces.

Centralized Clocking Mode

The Enhanced SCB SCBE on the MX240, MX480, and MX960 routers supports a Stratum 3 clock module. This clock module functions as a centralized point within the chassis for clock monitoring, filtering, holdover, and selection. It has only one external clock interface.

The Enhanced SCB SCBE2 on the MX240, MX480, and MX960 routers supports two external clock interfaces external-0/0 and external-1/0. The external-0/0 interface refers to the external interface on the SCB in slot 0 and the external 1/0 interface refers to the external interface on the SCB in slot 1.

In SONET/SDH networks, the routers use the best-quality clock available in the network. The quality level of various clock sources in the network is determined by monitoring the Synchronization Status Messages (SSMs) from the clock sources. An SSM occupies a fixed location in the SONET frame. On Ethernet networks that use Synchronous Ethernet for clock synchronization, the SSM is not a part of the timing signal. The SSM is carried in the Ethernet packets that flow in the Ethernet Synchronization Message Channel (ESMC). By interpreting the SSM values, the router determines the clock quality associated with the clock source, and performs its clock selection accordingly. The ESMC messages transmit the clock quality of the line timing signal in the form of the SSM TLV that is part of the ESMC packet.

Note that the clock in the router goes into holdover mode in the absence of any clock sources with best quality level and in turn uses the timing information stored in its buffer to synchronize itself.

The following processes play a crucial role during external synchronization of the clock sources in the control board. Note that PTX Series routers need two best clock sources that act as primary and secondary clock sources, whereas MX Series routers need only one best clock source.

• The clock sync process (clksyncd) performs the clock selection and participates in ESMC message exchange. For clock selection, in the absence of user-configured primary or secondary clock sources, the clksyncd runs a clock selection algorithm and selects the two best clocks available as the primary and secondary clock sources, respectively, for a PTX Series router or selects a best clock for an MX Series router. The clksyncd also sends out periodic ESMC packets to transmit its clock’s quality level to the other routers in the network—this is specified in the SSM TLV in the ESMC packet—and receives ESMC packets from other clock sources and tracks the received clock signal quality level. ESMC packets are received on all the interfaces that are configured as clock sources. ESMC packets are also transmitted to the clock-source interfaces on other routers, as well as to the interfaces that are configured to receive ESMC packets on other routers.

• The chassis process (chassisd) is responsible for interfacing with the Enhanced Switch Control Board (SCBE) on MX Series routers and Centralized Clock Generator (CCG) on PTX Series routers. It monitors the clock quality and assists SCBE or the CCG to determine the clock source with the best quality level. When it detects clock quality deterioration, it informs clksyncd to select another primary clock source. After clock selection chassisd is updated with the latest clock source information. Note that in the absence of user-configured primary and secondary clock sources on PTX Series routers, the clock sources are selected through the clock algorithm and chassisd is updated with the latest clock information. Consequently, a new interprocess connection is established between chassisd and clksyncd.

• The periodic packet management process (ppmd) performs periodic transmission of ESMC packets to others routers in the network. It also receives incoming ESMC packets from other routers. The ppmd filters out repetitive ESMC packets to reduce packet flows between ppmd and clksyncd.

The following explains a simple clock selection process using ESMC packets:

• The Synchronous Ethernet (line timing) signal is an Ethernet physical layer signal that is received on the Ethernet interface. ESMC is a Layer 2 Ethernet packet. The Synchronous Ethernet signal and the ESMC packets are received on the Ethernet interface of the router.

• The received Synchronous Ethernet signal is sent to the clock hardware in the SCBE or in the CCG, whereas the ESMC packets—with the quality level—is directed to the clksyncd.

• The clock selection algorithm in clksyncd selects the best clock signal based on the quality level in the ESMC packet from one of the interfaces that is configured as a clock source. On PTX Series routers, the algorithm also selects the next best—when available—clock as the secondary clock.

• The best clock information is transmitted to the chassisd, which in turn generates a command to the clock hardware to use the best clock as the reference clock. On PTX Series routers, both primary and secondary clocks are used..

• The reference clock uses the best—primary in PTX Series routers—clock signal as the system clock that is used to generate Synchronous Ethernet signal to transmit on all its interfaces.

• The ESMC transmit module in clksyncd is notified of the quality level corresponding to the best—primary—clock. This quality level is used for ESMC packets that are transmitted out of the router.

• ESMC packets are transmitted on all the source interfaces and on those interfaces that are configured as esmc-transmit interfaces.

The centralized mode is applicable to mobile backhaul infrastructures and for network transition from traditional TDM to Ethernet network elements with the support of Synchronous Ethernet.

Clock Selection

Configuring external clock synchronization requires making clock selection, quality level, and priority considerations. The clock selection algorithm is used to pick the two best clock sources—primary and secondary—from among the various sources.

The clock selection algorithm is on the basis of the system configuration and execution criteria such as quality level, priority, hardware restrictions, and so on, and is achieved using the following logic and restrictions:

• The following parameters must be configured irrespective of whether the quality level is enabled or not (You can set the quality level with the set chassis synchronization source interfaces external quality-level quality-level configuration command at the [edit] hierarchy level.):

  • Quality level must be configured for nonexternal clocks.

  • In the case of option-1, the quality level must be configured for the external clocks.

  • In the case of option-2, the default quality level for the external clocks is QL_STU.

  The synchronous Ethernet Equipment Clock (EEC) synchronization networking types option-1 and option-2 map to G.813 option 1 (EEC1) and G.812 type IV clock (EEC1) standards, respectively, and can be configured at the [edit chassis synchronization] hierarchy level.

• When the quality-mode-enable statement is included at the [edit chassis synchronization] hierarchy level, the received quality level must be equal to or better than the configured quality level for that particular source, otherwise that source is not considered for clock selection. This is so that a downstream client is guaranteed clock quality of a certain level. (Note that the term certain level here denotes the configured quality level.)

• Configuring the quality level for a Synchronous Ethernet interface is optional when the quality-mode-enable and the selection-mode received-quality statements are included at the [edit chassis synchronization] hierarchy level.

  The default quality level value for a Synchronous Ethernet interface is:

  • SEC for the option-1 network type.

  • ST3 for the option-2 network type.

• Configuring the priority statement is optional. When not specified, the external-a interface has a higher default priority than the external-b interface, and the external-b interface has a higher default priority than Ethernet-based sources such as ge or xe clock sources, which have the lowest default priority.

  Note:

  Configured priority is higher than any default priority.

• During clock selection:

  • The active source with the highest quality level is selected.

  • The configured (or default) quality level of the selected clock source is used for Ethernet Synchronization Message Channel (ESMC). In order to receive or transmit ESMC messages out of an interface, at least one logical interface must be configured on that interface.

  • Table 1 explains a few scenarios that must be taken into consideration during clock selection:

    Table 1: Clock Selection Scenarios

    If	Then
    Two or more sources have the same quality level.	The source with highest priority is selected.
    Two or more sources have the same quality level and priority.	The current active source, if any, among these sources is selected.
    Two or more sources have the same quality level and priority, and none of these is currently active.	Any one of these sources is selected.
    Primary clock source is ge|xe-x/y/z, where y is even (0 or 2).	The secondary clock source cannot be ge|xe-x/y/* or ge|xe-x/y + 1/*. For example, if ge-1/2/3 is the primary clock source, then the secondary clock source cannot be ge-1/2/* or ge-1/3/* for an MX80, MX240, MX480, or an MX960 router.
    Primary clock source is ge|xe-x/y/z, where y is odd (1 or 3).	The secondary clock source cannot be ge|xe-x/y/* or ge|xe-x/y - 1/*. For example, if xe-2/3/4 is the primary clock source, then the secondary clock source cannot be xe-2/2/* or xe-2/3/* for an MX80, MX240, MX480, or an MX960 router.
    Primary clock source is ge|xe-x/y/z.	The secondary clock source cannot be ge|xe-x/y/* in the case of 12-port or 16-port 10-Gigabit Ethernet DPC on an MX Series router. For example, if ge-0/1/2 is the primary clock source, then ge-0/1/* cannot be the secondary clock source, but ge-0/0/* can be the secondary clock source.

On PTX Series routers, you can specify the primary and secondary clock sources provided the clock source meets the necessary qualification as set by the clock algorithm. However, in the absence of any user-selected clock source, the clock source with the best quality level is selected by the clock algorithm in the router. Note that the user selection is honored even when better quality level clock sources are available. You can select the clock source with the request chassis synchronization switch clock-source operational mode command. For more information, see request chassis synchronization switch.

The clock sources used as primary or secondary clock sources cannot originate from the same FPC.

Network Option

The clock type or network option is the synchronous Ethernet Equipment Clock (EEC) synchronization networking type. You can set the network option to one of the following values:

• option-1—This option maps to G.813 option 1 (EEC1).

• option-2—This option maps to G.812 type IV clock (EEC1).

To configure the clock type, execute the set chassis synchronization network-option (option-1 | option-2) configuration command at the [edit] hierarchy level.

Clock Mode

You can set the Synchronous Ethernet clock source to one of the following modes:

• free-run—In this mode, the free-running local oscillator is used as a clock source.

  Note:

  For MX80 routers, the free-run clock is provided by the local oscillator.

  For MX240, MX480, and MX960 routers with an SCB, the free-run clock is provided by the MPCs.

  For MX240, MX480, and MX960 routers with an SCBE or an SCBE2, the free-run clock is provided by the local oscillator.

• auto-select—In this mode, the best external clock source is selected.

By default, the auto-select option is selected.

To configure the clock mode, execute the set chassis synchronization clock-mode (free-run | auto-select) configuration command at the [edit] hierarchy level.

Quality Mode

When the quality-mode-enable statement is included at the [edit chassis synchronization] hierarchy level, the system ascertains that the clock selection algorithm uses both quality and priority of the clock sources to select the best clock source for clock synchronization. When the quality-mode-enable statement is not included, only the priority of the clock source is taken into account by the algorithm.

To enable the synchronization quality mode, include the quality-mode-enable statement at the [edit chassis synchronization] hierarchy level.

The Synchronous Ethernet ESMC quality mode is disabled by default. The Synchronous Ethernet ESMC quality mode is disabled when the quality-mode-enable statement is not included.

Selection Mode

You can specify whether the clock source selection must use the configured or the received ESMC or SSM quality level for a qualifying interface. In both selection modes, the interface qualifies for clock source selection only when the received ESMC or SSM quality level on the interface is equal to or greater than the configured ESMC or SSM quality level for the interface.

The selection modes are:

• configured-quality—In this mode, the clock source selection algorithm uses the ESMC or SSM quality level configured for a qualifying interface.

• received-quality—In this mode, the clock source selection algorithm uses the ESMC or SSM quality level received on the qualifying interface.

To configure the clock source algorithm selection mode, execute the set chassis synchronization selection-mode (configured-quality|received-quality) configuration command at the [edit] hierarchy level.

Hold Interval

You can set the chassis synchronization wait time after a change in configuration, the clock selection wait time after reboot of the router, and the switchover wait time after a switchover of SCB before selecting the new clock source. The hold interval options are:

• configuration-change—In this mode, the wait time for clock selection after a change in configuration (clock synchronization configuration) can be set from 15 seconds through 60 seconds.

• restart—In this mode, the wait time for clock selection after reboot of the router can be set from 60 seconds through 180 seconds.

• switchover—In this mode, the switchover wait time after clock recovery can be set from 30 seconds through 60 seconds.

To set the hold interval, execute the set chassis synchronization hold-interval (configuration-change | restart | switchover) seconds configuration command at the [edit] hierarchy level.

The default switchover wait time is 30 seconds and the default restart wait time is 120 seconds.

Switchover Mode

You can set the switchover mode to switch the clock from a lower quality source to higher quality source or to use the current clock source only. You can configure the switchover mode to one of the following:

• non-revertive—In this mode, the router uses the current clock source as long as it is valid.

• revertive—In this mode, the router automatically switches from a lower to a higher quality clock source whenever the higher clock source becomes available.

The default mode is revertive mode.

To configure the switching mode, execute the set chassis synchronization switchover-mode (revertive | non-revertive) configuration command at the [edit] hierarchy level.

Clock Source

You can specify the parameters that must be considered by the clock selection algorithm while selecting the best clock source. The parameters include the quality level value, the priority of the clock source, the request criteria, and the wait time to restore the interface signal to up state. You must specify these parameters on the external clock interfaces or other qualifying interfaces—which are connected to valid clock sources—to select the best clock source on the basis of the timing messages that are received on these interfaces.

For an SCBE, you can configure only one external interface and configure multiple Ethernet interfaces as needed.

On SCBE2, you can configure two external interfaces—external-0/0 and external-1/0—and configure multiple Ethernet interfaces as needed.

To configure the clock source, execute the set chassis synchronization source interfaces interface-name configuration command. You can also configure the clock source with the set chassis synchronization source interfaces external at the [edit] hierarchy level, where the external option refers to an external clock interface.

To specify the clock source for an interface, you must set the following options:

• priority—You can set the user priority for the selected clock source from 1 through 5.

  To set the synchronization source priority for the selected clock source, execute the set chassis synchronization source interfaces interface-name priority number configuration command or the set chassis synchronization source interfaces external priority number configuration command at the [edit] hierarchy level.

• request—You can set the clock selection request criterion as one of the following:

  • force-switch—With this option, you can force the SCB to switch to a clock source you prefer on a particular interface (that is you can select a clock source on an interface overriding the algorithm), provided the source is enabled and not locked out. Only one configured source can be force-switched.

  • lockout—With this option configured, the clock source is not to be considered by the selection process. Lockout can be configured for any source.

  To configure these options, execute the set chassis synchronization source interfaces interface-name request (force-switch|lockout) configuration command or the set chassis synchronization source interfaces external request (force-switch|lockout) configuration command at the [edit] hierarchy level.

• wait-to-restore—You can set the wait-to-restore time for each interface. When an interface’s signal transitions out of the signal fail state, it must be fault-free for the wait-to-restore time before it is again considered by the clock selection process. You can configure the interface signal upstate time—wait time before opening the interface to receive ESMC messages—from 0 through 12 minutes. The default time is 5 minutes. When the ESMC clock’s EEC quality level (QL) mode is enabled, it sends a signal failure to the clock selection process during the wait-to-restore time. After the wait-to-restore time ends, a new quality level value is sent to the clock selection process.

  To configure the wait-to-restore time, execute the set chassis synchronization source interfaces interface-name wait-to-restore minutes configuration command or the set chassis synchronization source interfaces external wait-to-restore minutes configuration command at the [edit] hierarchy level.

• hold-off-time—You can configure hold-off time for Synchronous Ethernet interfaces and external clock source interfaces to prevent rapid successive switching between signal fail states. If an interface goes down, hold-off time delays short signal failures from being sent to the clock selection process.

  Note:

  During the hold-off time period, if the clock synchronization process restarts, hold-off time is not considered.

  If you configure hold-off time when the ESMC clock’s EEC QL mode is enabled, the configured quality level is used in the clock selection process during the hold-off time period. During the hold-off time period, the external clock source appears in a locked state until the hold-off time period ends. After the hold-off time period ends, a signal failure is sent to the clock selection process.

  You can configure hold-off time for a range of 300 through 1800 milliseconds. The default hold-off time is 1000 milliseconds.

  To configure hold-off time, execute the set chassis synchronization source interfaces interface-name hold-off-time configuration command at the [edit] hierarchy level.

  Note:

  When a link goes down and comes back up within the configured hold-off time in a clocking hybrid mode configuration (the combined operation of Synchronous Ethernet and Precision Time Protocol) that includes the protocols ptp slave convert-clock-class-to-quality-level configuration statement at the [edit] hierarchy level, the phase might not get locked before the timer expires. This might result in a degradation of clock quality level.

• quality—You can set the ESMC clock’s EEC quality level as prc, prs, sec, smc, ssu-a, ssu-b, st2, st3, st3e, st4, stu, or tnc. Both option I and option II SSM quality levels are supported. Table 2 explains the quality level values.

  Table 2: Quality Levels

  Quality Level	Description
  prc	Timing quality of a primary reference clock (option-1 only).
  prs	Clock traceable to a primary reference source (option-2 only).
  sec	Timing quality of an SDH equipment clock (option-1 only).
  smc	Clock traceable to a self-timed SONET clock (option-2 only).
  ssu-a	Timing quality of a type I or IV client clock (option-1 only).
  ssu-b	Timing quality of a type VI client clock (option-1 only).
  st2	Clock traceable to Stratum 2 (option-2 only).
  st3	Clock traceable to Stratum 3 (option-2 only).
  st3e	Clock traceable to Stratum 3E (option-2 only).
  st4	Clock traceable to Stratum 4 free-run (option-2 only).
  stu	Clock traceable to an unknown quality (option-2 only).
  tnc	Clock traceable to a transit node clock (option-2 only).

  Note:

  When the quality level is not configured and no ESMC messages are received by the clock source, then the quality level is set to DNU for option-1 and DUS for option-2. You can configure the network options, option-1 and option-2 at the [edit chassis synchronization network-option] hierarchy level.

  To avoid source looping on the selected active source—primary or secondary source, whichever is active—even when ESMC transmit is not enabled, a DNU ESMC message is sent out when the network-option statement is configured as option-1, and a DUS ESMC message is sent out when the network-option statement is configured as option-2. This is applicable only for clock sources configured on the Ethernet interfaces.

  To configure the quality level, execute the set chassis synchronization source interfaces interface-name) quality-level (prc | prs |sec | smc | ssu-a | ssu-b | st2 | st3 | st3e | st4 | stu | tnc) configuration command or the set chassis synchronization source interfaces external quality-level (prc | prs |sec | smc | ssu-a | ssu-b | st2 | st3 | st3e | st4 | stu | tnc) configuration command at the [edit] hierarchy level.

ESMC Packet Transmit

You can enable all the interfaces or configure one or more qualifying interfaces on which to permit ESMC transmit messages by executing the set chassis synchronization esmc-transmit interfaces (all |interface-name) configuration command at the [edit] hierarchy level.

Global Wait To Restore

You can globally configure the time in minutes for source ports to be up before opening the Ethernet Synchronization Message Channel (ESMC) for messages. When a port’s signal transitions out of the signal fail state, it must be fault-free for the global wait-to-restore time before it is again considered by the clock selection process.

To configure the global wait-to-restore time, include the global-wait-to-restore statement at the [edit chassis synchronization] hierarchy level.

To override the global wait-to-restore time on a specific interface, include the wait-to-restore statement at the [edit chassis source interfaces (external-a | external-b | interface interface-name)] hierarchy level.

Maximum Transmit Quality Level

To configure the maximum transmit quality level for SCBE2 as prc, prs, sec, smc, ssu-a, ssu-b, st2, st3, st3e, st4, stu, or tnc, execute the set chassis synchronization max-transmit-quality-level quality-level configuration command at the [edit] hierarchy level.

You can configure the max-transmit-quality-level statement on SCB and SCBE.

For GPS external output, when you configure the maximum transmit quality level as PRC and router is rebooted, no valid output is obtained from SCBE. However, when the maximum transmit quality level is configured to any other quality level other than PRC and the router gets rebooted, then the SCBE works normally.

Interfaces with Upstream Clock Source

You can configure the external interface to operate with a connected router for a clock source. This external interface can be configured for a clock source, which then becomes a candidate for selection as the chassis clock source by the clock source selection algorithm. You can configure several options for the external clock source interface on the SCBE and for the two external clock source interfaces on the SCBE2.

The options include E1 interface options, pulse-per-second option, the signal type for the provided reference clocks, and the T1 interface options at the [edit chassis synchronization interfaces external] hierarchy level.

The following sections explain the clock source interface parameters in detail:

• E1 Interface Options
• Pulse Per Second
• Signal Type
• T1 Interface Options

External Output Interface

You can set several options for the external clock output interface for SCBE or for the two external clock output interfaces for SCBE2.

The options include disabling the holdover mode; configuring a minimum quality threshold; configuring a mode to select a clock source; configuring the transmit quality level to DNU or DUS; and disabling wander filtering at the [edit chassis synchronization output interfaces external] hierarchy level for SCBE or at the [edit chassis synchronization output interfaces (external0-0 | external-1/0)] hierarchy level for SCBE2.

The following sections explain the external output interface parameters in detail:

• Holdover Mode
• Minimum Quality
• Source Mode
• Transmit Quality Level
• Wander Filter

Clock Synchronization Ports

You can set the time-of-day-format statement as an ASCII string on SCBE and SCBE2 by executing the set chassis synchronization port auxiliary client time-of-day-format ascii string configuration command at the [edit] hierarchy level.

The time of day (TOD) format is specified as a string of ASCII characters. The TOD format string contains information that specifies which ASCII characters to match, which ASCII characters to ignore, and which ASCII characters to translate to particular time units (such as month, day, hour, minute, and so on).

The TOD format string specifies how the incoming string is to be parsed so that the information embedded can be extracted. The format of the TOD option can be executed with the set chassis synchronization port auxiliary time-of-day-format ascii string configuration command at the [edit] hierarchy level, where the format of the data string is $GPRMC,%hh%mm%ss,^,^^^^.^^,^,^^^^^^^^,^,^^^^^,^^^^^,%DD%MM%YY,^^^^^,^*^^.

Table 3 explains pattern-matching characters used in the TOD data string.

There are several patterns that can be received by a router. The following pattern shows an example of a received TOD data string (as defined in the National Marine Electronics Association (NMEA) 0183 standard. The data string is called the Recommended Minimum Specific GPS/Transit Data (RMC) message.) and Table 4 explains it in detail.

MIC-Level Framing Mode

You can configure the LAN framing mode on the 10-Gigabit Ethernet MIC with XFP by executing the set chassis fpc fpc-slot pic pic-slot framing lan at the [edit] hierarchy level.

Note that to operate in LAN framing mode on the 10-Gigabit Ethernet MIC with XFP, you must configure the interface framing mode on the MIC interface. Execute the set interfaces xe-fpc/pic/port framing-mode (lan-phy | wan-phy) configuration command at the [edit] hierarchy level, where the lan-phy option denotes a 802.3ae 10-Gbps LAN-mode interface and the wan-phy option denotes a 802.3ae 10-Gbps WAN-mode interface.

Clock Source Selection Algorithm

The clock source selection algorithm uses the following logic and restrictions:

• QL must be configured for non-external clocks, whether or not QL is enabled.

• For network-option option-1, QL must be configured for external clocks (gps or bits) whether or not QL is enabled.

• In the case of network-option option-2, the default QL for the external clocks is QL_STU, whether or not QL is enabled.

• Configuring priority is optional. When not specified, gps has a higher default priority than bits, and bits has a higher default priority than Gigabit Ethernet, 10-Gigabit Ethernet, and T1 or E1 clock, which have the lowest default priority.

• When QL is enabled, the received QL must be equal to or better than the configured QL for that particular source or else that source will not be considered for clock selection. This is so that a downstream client is guaranteed clock quality of a certain level (that “certain level” being the configured QL).

During clock selection:

• The active source with the highest QL is selected.

• If QL is the same for two or more sources, then the source with the highest priority is selected.

• If two or more sources have the same QL and priority, then the currently active source, if any, among these sources is selected.

• If two or more sources have the same QL and priority, and none of these is currently active, then any one of these may be selected.

• If selection-mode is configured quality, then the configured (or default) QL of the selected clock source is used for transmitting ESMC. If selection-mode is received quality, then the received QL of the selected clock source is used for ESMC transmit.

• In order to receive or transmit ESMC messages out of an interface, at least one logical interface should be configured on that interface. If the interface is currently not configured with a logical interface, you may do so using the set interfaces interface-name unit 0 statement at the edit hierarchy level.

The clock source selection algorithm is triggered by the following events:

• Changes in the received ESMC SSM quality level (QL)

• Configuration changes. For example, the addition or deletion of a clock source, a change to the QL mode, and so on.

• Signal failure detected on the currently selected source.

When the router is configured with automatic clock selection, the system chooses up to two best upstream clock sources. The system then uses the clock recovered from one of the sources to lock the chassis clock. If an upstream clock with acceptable good quality is not available or if the system is configured in free-run mode, the system uses the internal oscillator.

Clock Selection and Quality Level

Automatic clock selection supports two modes: QL enabled and QL disabled.

• QL disabled— In this mode, the best clock is selected based on the configured ESMC SSM QL. If the QL of the configured clocks are equal, the clock selection is based on the configured priority. If both the configured QL and priority are equal, one of the sources is randomly selected. Absence of the quality-mode-enable statement at the [edit chassis synchronization] hierarchy level means that QL is disabled.

  Note:

  The default setting is QL disable.

• QL enabled—In this mode, the best clock is selected based on the incoming ESMC SSM QL as long as the incoming QL is at least as good as the source’s configured QL. If the QLs are equal, the clock selection is based on the configured priority. If both the received QL and the priority are equal, one of the sources is selected randomly.

Selection Mode for the Incoming ESMC Quality

Depending on the configuration, the clock source selection algorithm uses the configured or received ESMC SSM quality level for clock selection. In both configured and received selection modes, the interface qualifies for clock source selection only when the received ESMC SSM quality level on the interface is equal to or greater than the configured ESMC SSM quality level for the interface.

Automatic Clock Selection for ACX Series Routers

The ACX Series Universal Metro routers support external clock synchronization and automatic clock selection for Synchronous Ethernet, T1 or E1 line timing sources, and external inputs. Configuring external clock synchronization and automatic clock selection requires making clock selection, quality level (QL), and priority considerations. The clock source selection algorithm is used to pick the two best upstream clock sources from among all the various sources, based on system configuration and execution criteria such as QL, priority, and hardware restrictions.

With automatic clock selection, the system chooses up to two best upstream clock sources. The system then uses the clock recovered from one of the sources to lock the chassis clock. If an upstream clock with acceptable good quality is not available or if the system is configured in free-run mode, the system uses the internal oscillator. The following automatic clock selection features are supported for Synchronous Ethernet, T1 or E1 line timing sources, and external inputs:

Automatic clock selection is supported on the ACX Series routers. Automatic clock selection of the best quality clock source is based on the Ethernet Synchronization Message Channel (ESMC) Synchronization Status Message (SSM) quality level, the configured quality level, and the priority. To configure automatic clock selection, include the auto-select option at the [edit chassis synchronization] hierarchy level. You can also configure the chassis to lock to the free-running local oscillator, which is the Stratum 3E oscillator, by including the free-run option at the [edit chassis synchronization] hierarchy level. The auto-select option enables the clock source selection algorithm to run. The clock source selection algorithm is triggered by the following events:

• Signal failure detected on the currently selected source

• Changes in the received Ethernet Synchronization Message Channel (ESMC) Synchronization Status Message (SSM) quality level (QL)

• Configuration changes. For example, the addition or deletion of a clock source, a change to the QL mode, and so on.

Automatic clock selection supports two modes on the ACX Series router: QL enabled and QL disabled. To configure QL mode, include the quality-mode-enable statement at the [edit chassis synchronization] hierarchy level.

• QL disabled—The default setting is disable, which means that when the quality-mode-enable statement is not configured, QL is disabled. In this mode, the best clock is selected based on the configured ESMC SSM QL. If the QL of the best clocks are equal, the clock selection is based on the configured priority. If both the configured QL and priority are equal, one of the sources is randomly selected.

• QL enabled—In this mode, the best clock is selected based on the incoming ESMC SSM QL as long as the incoming QL is at least as good as the source’s configured QL. If the QLs are equal, the clock selection is based on the configured priority. If both the received QL and the priority are equal, one of the sources is selected randomly.

Interface and Router Clock Sources Overview

When configuring the router, you can configure the transmit clock on each interface; the transmit clock aligns each outgoing packet transmitted over the router’s interfaces. For both the router and interfaces, the clock source can be the router’s internal Stratum 3 clock, which resides on the control board, or an external clock that is received from the interface you are configuring. For example, interface A can transmit on interface A’s received clock (external, loop timing) or the Stratum 3 clock (internal, line timing). Interface A cannot use a clock from any other source.

By default, each interface uses the router’s internal Stratum 3 clock. To configure the clock source of each interface, include the clocking statement at the [edit interfaces interface-name] hierarchy level:

System reference clocks can be generated from different system components, depending on the router type. For example, Figure 1 illustrates the different clock sources on the M120 router.

Figure 1: M120 Router Clock Sources

Configure an External Clock Synchronization Interface

The M40e, M120, M320, T640, and T1600 routers support an external synchronization interface that can be configured to synchronize the internal Stratum 3 clock to an external source, and then synchronize the chassis interface clock to the external source.

This feature can be configured for external primary and secondary interfaces that use Building Integrated Timing System (BITS) or SDH Equipment Timing Source (SETS) timing sources, or an equivalent quality timing source. When internal timing is set for SONET/SDH, Plesiochronous Digital Hierarchy (PDH), and digital hierarchy (DS1) interfaces on the Physical Interface Cards (PICs), the transmit clock of the interface is synchronized to BITS/SETS timing and traceable to timing within the network.

Routers and switches that support an external clock synchronization interface include:

• M40e, M120, and M320 routers

• T640 and T1600 routers

To configure external synchronization on the router, include the synchronization statement at the [edit chassis] hierarchy level:

Use the synchronization statement options to specify a primary and secondary timing source. To do this, configure the following options:

• For the M120 and M320 routers, specify a signal type mode for interfaces, either t1 or e1. For the M40e, T640, and T1600 routers, only the t1 signal type mode is supported. The default setting is t1.

• For the T640 and T1600 routers, external clock interfaces are supported on the SONET Clock Generators (SCG-T-EC). The external clock interfaces on the SONET Clock Generators (SCG-T) are not supported.

• Specify the switching mode as revertive if a lower-priority synchronization can be switched to a valid, higher-priority synchronization.

• For the M320 router, specify that a single signal should be wired to both Control Boards (CBs) using a Y-cable. For the M40e router, the signal is wired to the CIP and Y-cable functionality is embedded in this system.

  The y-cable-line-termination option is not available on the M40e, M120, T640, and T1600 routers.

• Control whether the diagnostic timing signal is transmitted.

  The transmitter-enable option is not available on the M120, T640, and T1600 routers.

• Set a validation interval. The validation-interval option validates the synchronized deviation of the synchronization source. If revertive switching is enabled and a higher-priority clock is validated, the clock module is directed to the higher-priority clock, and all configured and active synchronizations are validated. The validation timer resumes after the current validation interval expires. The validation interval can be a value from 90 through 86,400 seconds. The default value is 90 seconds. For the M120 router, the range for the validation-interval option is 30 through 86,400 and the default value is 30.

• Specify the primary external timing source by using the primary (external-a | external-b) statement.

• Specify the secondary external timing source by using the secondary (external-a | external-b) statement.

Getting Started to Configure Clock Synchronization on PTX Series Routers

System clocking on PTX Series Packet Transport Routers is controlled by a Centralized Clock Generator (CCG). The CCG is capable of deriving a primary clock from a valid source and synchronizing all interfaces on the chassis to this primary clock.