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Junos® OS Documentation for ACX, M, MX, PTX, and T Series Routers, Release 12.3
Overview of Channelized IQ Interfaces
Guidelines for Configuring Channelized IQ Interfaces
Frame Relay DLCI Limitations for Channelized IQ Interfaces
System Requirements for Channelized IQ Interfaces
Terms and Acronyms for Channelized IQ Interfaces
Roadmap for Configuring Channelized IQ Interfaces
Configuring a Clear Channel on a Channelized IQ Interface
Configuring Single-Level Channels on a Channelized IQ Interface
Configuring Multilevel Channels on a Channelized IQ Interface
Configuring a Class-of-Service Scheduler Map
Associating the Scheduler with a DLCI on a Channelized IQ Interface
Scheduler Limitations for Channelized IQ Interfaces
Verifying Class-of-Service Schedulers on Channelized IQ Interfaces
Roadmap for Channelized IQ Interface Configuration Examples
Merging Examples
Example: OC12 Clear Channel on a Channelized OC12 IQ Interface
Example: Complex Configuration for a Channelized OC12 IQ Interface
Example: Converting a Channelized OC12 IQ PIC to a Channelized STM4 IQ Interface
Example: Channelized OC3 IQ Interface Configuration
Example: Channelized DS3 IQ Interface Configuration
Example: Channelized T1 IQ Interface Configuration
Example: Channelized STM1 IQ Interface Configuration
Example: Channelized E1 IQ Interface Configuration
Example: DLCI Class of Service on a Channelized IQ Interface Configuration
show class-of-service interface
show class-of-service forwarding-table
show interfaces controller (Channelized E1 IQ)
show interfaces controller (Channelized OC12 IQ and IQE)
show interfaces controller (Channelized OC3 IQ and IQE)
show interfaces controller (Channelized STM1 IQ)
show interfaces controller (Channelized T1 IQ)
show interfaces controller (Channelized T3 IQ)
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