Related Documentation
- M, MX, T Series
- Roadmap for Configuring Channelized IQ Interfaces
- Roadmap for Channelized IQ Interface Configuration Examples
- Additional Information
- Channelized IQ Interfaces
Overview of Channelized IQ Interfaces
Channelized interfaces allow service providers to customize bandwidth to satisfy the needs of their customers. Whether the subscriber needs DS0, T1, fractional T1, E1, fractional E1, E3, T3, STM1, OC3, or OC12 service, a channelized interface can provide the necessary bandwidth today and can be reconfigured to support the customer’s expanding network tomorrow. Standard channelized interfaces have been available on Juniper Networks routing platforms since JUNOS Release 3.4.
The original channelized interfaces for Juniper Networks M-series routers are available in the following models:
- 1-port Channelized OC12 PIC
- 10-port Channelized E1 PIC
- 1-port Channelized STM1 PIC
- 4-port Channelized DS3 PIC
- 1-port and 2-port multichannel Channelized DS3 PIC
These channelized interfaces provide a single level of channelization and require at both the [edit chassis] and the [edit interfaces] hierarchy levels. Most configuration options must be set on channel 0 and apply to all channels on these channelized interfaces.
The new channelized interfaces with intelligent queuing offer several advantages over the original channelized interfaces:
- Complete configuration tasks for channelized IQ interfaces are now centralized at the [edit interfaces] hierarchy level.
- Multiple levels of channelization are now possible with channelized IQ interfaces. For example, a channelized OC12 IQ interface can be divided into channelized OC1 interfaces, then subdivided into channelized T1 interfaces, and further split into NxDS0 channels.
- You can now configure interface statements, such as clocking, on individual channels rather than configuring them on channel 0 for all channels at the same hierarchy level.
- Class-of-service (CoS) processing now occurs on the PIC for channelized IQ interfaces rather than in the FPC.
The following M-series and T-series PICs support channelized interfaces with intelligent queuing:
- 1-port Channelized OC12 IQ PIC
- 1-port Channelized OC3 PIC
- 4-port Channelized DS3 IQ PIC
- 10-port Channelized T1 IQ PIC
- 10-port Channelized E1 IQ PIC
- 1-port Channelized STM1 IQ PIC
To determine which PIC is installed, issue the show chassis hardware command:
user@RouterA> show chassis hardware
Hardware inventory: Item Version Part number Serial number Description Chassis 20070 M160 Midplane REV 03 710-001245 AB4123 FPM CMB REV 02 710-001642 AB3266 FPM Display REV 02 710-001647 AB3038 CIP REV 04 710-001593 AB3276 PEM 0 Rev 03 740-001243 KM28410 DC PEM 1 Rev 03 740-001243 LF21558 Power Entry Module PCG 0 REV 03 710-001568 AB3006 PCG 1 REV 02 710-001568 AB2992 Routing Engine 0 20000005dfae3a01 RE-2.0 MCS 0 REV 04 710-001226 AB3208 MCS 1 REV 04 710-001226 AB3212 SFM 0 SPP REV 06 710-001228 AB3103 SFM 0 SPR REV 01 710-002189 AB2936 Internet Processor II SFM 1 SPP REV 07 710-001228 AG2634 SFM 1 SPR REV 03 710-002189 AE3503 Internet Processor II SFM 2 SPP REV 06 710-001228 AB2976 SFM 2 SPR REV 01 710-002189 AB2938 Internet Processor II SFM 3 SPP REV 06 710-001228 AB5826 SFM 3 SPR REV 01 710-002189 AB2917 Internet Processor II FPC 0 REV 03 710-003947 HE0614 E-FPC Type 1 CPU REV 01 710-004600 AT3217 PIC 0 REV 03 750-005636 BE1826 4x CHDS3 IQ
PIC 1 REV 07 750-003846 HG5572 1x 800M Crypto PIC 2 REV 01 750-004507 BA5341 10x CE1-NxDS0 PIC 3 REV 06 750-003009 AM6929 4x CT3
FPC 1 REV 03 710-003309 AD9434 E-FPC Type 2 CPU REV 05 710-001217 AH2707 PIC 2 REV 05 750-001900 AD5738 1x OC-48 SONET, SMSR PIC 3 REV 04 750-003737 BC1106 4x G/E, 1000 BASE-SX
Related Documentation
- M, MX, T Series
- Roadmap for Configuring Channelized IQ Interfaces
- Roadmap for Channelized IQ Interface Configuration Examples
- Additional Information
- Channelized IQ Interfaces
Published: 2012-11-28
Related Documentation
- M, MX, T Series
- Roadmap for Configuring Channelized IQ Interfaces
- Roadmap for Channelized IQ Interface Configuration Examples
- Additional Information
- Channelized IQ Interfaces