Supported Platforms
Related Documentation
Clock Sources for PTX Series Packet Transport Routers
System clocking on PTX Series Packet Transport Routers is controlled by a Centralized Clock Generator (CCG). The CCG is capable of deriving a master clock from a valid source and synchronizing all interfaces on the chassis to this master clock. The CCG plugs into the rear of the chassis. A pair of CCGs installed in the chassis provide a redundant fallback option.
PTX Series Packet Transport Routers can use an internal clock source or it can extract clocking from an external source.
Clock sources and specifications include:
- The PTX Series Packet Transport Router clock is a Stratum 3E-compliant clock with Free Run +/- 4.6 ppm/20 years, Holdover +/- 0.01 ppm/24 hours, and Drift +/- 0.001 ppm/24 hours.
- The internal clock is based on Freerun OCXO with +/- 10 ppb accuracy.
- External clocking includes a choice of GPS-based clock recovery (5 MHz and 10 MHz) or BITS-T1/E1 Line synchronization (1.544 MHz and 2.048 MHz)
- Synchronous Ethernet is supported based on the ITU G.8261
and G.8262 specifications with line timing from the 10-Gigabit Ethernet,
40-Gigabit Ethernet, or 100-Gigabit Ethernet interface.
Synchronous Ethernet is a key requirement for circuit (emulation) services and mobile radio access technologies. Synchronous Ethernet supports sourcing and transfer of frequency for synchronization purposes for both wireless and wireline services and is primarily used for mobile backhaul and converged transport.
Figure 1: Clocking Example for PTX Series Packet Transport Routers
In this example, the primary clock source is configured as interface et-7/1/1 and the secondary clock source is configured as gps1.
