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Configuring an External Clock Synchronization Interface for PTX Series Packet Transport Routers

The PTX Series Packet Transport Routers support an external synchronization interface that can be configured to synchronize the internal Stratum 3 clock to an external source, and then synchronize the chassis interface clock to that source.

This feature can be configured for external primary and secondary interfaces that use building-integrated timing system (BITS), SDH Equipment Timing Source (SETS) timing sources, or an equivalent quality timing source. On the Physical Interface Cards (PICs), the transmit clock of the interface is synchronized to BITS/SETS timing and is traceable to timing within the network.

The PTX Series Packet Transport Routers include a Centralized Clock Generator (CCG) that is used to generate systemwide interface timing signals. The CCG:

• Provides a synchronous Ethernet clock source to the chassis.
• Accepts a BITS clock from CCG bulkhead to use as the basis for the Stratum clock source.
• Accepts an RX recovered clock from an FPC to use as input for the Stratum clock source.

The sources can be BITS, GPS, freerunning, or RX recovered line timing.

To configure a recovered clock for an FPC, include the recovered-clock statement at the [edit chassis fpc slot-number pic pic-number] hierarchy level:

To configure external synchronization on the router, include the synchronization statement at the [edit chassis] hierarchy level:

Use the synchronization statement options to specify a primary and secondary timing source. To do this, configure the following options:

• For the PTX Series Packet Transport Routers, specify a signal type mode for interfaces, either t1 or e1.
• Specify the switching mode as revertive if a lower-priority synchronization can be switched to a valid, higher-priority synchronization.
• Specify the primary external timing source by using the primary (fpc-slot-number | gps-0-10mhz | gps-0-5mhz | gps-1-10mhz | gps-1-5mhz |bits-a | bits-b) statement.
• Specify the secondary external timing source by using the secondary (fpc-slot-number | gps-0-10mhz | gps-0-5mhz | gps-1-10mhz | gps-1-5mhz |bits-a | bits-b) statement.

For the PTX 5000 Packet Transport Router, the supported clock sources are:

• fpc-0, fpc-1, fpc-2, fpc-3, fpc-4, fpc-5, fpc-6, or fpc-7.
• gps-0-10mhz, gps-0-5mhz, gps-1-10mhz, or gps-1-5mhz.
• bits-a or bits-b