Related Documentation
- M, MX, T Series
- Roadmap for Configuring Channelized IQ Interfaces
- Overview of Channelized IQ Interfaces
- Roadmap for Channelized IQ Interface Configuration Examples
- Additional Information
- Channelized IQ Interfaces Solutions Page
Configuring Single-Level Channels on a Channelized IQ Interface
You can subdivide a channelized interface directly into a set of large end channels. To configure part of a channelized IQ interface as a channel, include the partition statement at the [edit interfaces cxx-fpc/pic/port] hierarchy level. On a channelized OC12 IQ interface, use the oc-slice option to create slice sizes corresponding to the desired bandwidth. On a channelized E1 IQ interface, use the timeslots option to define NxDS0 channels or channel groups. On all channelized IQ interfaces, use the interface-type option to set the interface type (such as SONET OC3 or T3). Once the channel interfaces are established, you can configure them the same way as regular interfaces.
 | Note: One oc-slice in a channelized OC12 IQ interface partition is equivalent to one OC1/DS3-sized channel. If you add three slices together in sequence as a triplet, these pieces become an OC3-sized interface. However, you can configure triplets only with the following sequential slices: 1–3, 4–6, 7–9, 10–12. |
Related Documentation
- M, MX, T Series
- Roadmap for Configuring Channelized IQ Interfaces
- Overview of Channelized IQ Interfaces
- Roadmap for Channelized IQ Interface Configuration Examples
- Additional Information
- Channelized IQ Interfaces Solutions Page
Published: 2012-11-28
Related Documentation
- M, MX, T Series
- Roadmap for Configuring Channelized IQ Interfaces
- Overview of Channelized IQ Interfaces
- Roadmap for Channelized IQ Interface Configuration Examples
- Additional Information
- Channelized IQ Interfaces Solutions Page
