Configuring Channelized OC12/STM4 IQ Interfaces (SDH Mode)
The Channelized OC12 IQ PIC configured for SDH mode creates a single channelized STM4 interface. You can configure this interface as unpartitioned using the no-partition statement at the [edit interfaces cstm4-fpc/pic/port] hierarchy level to create a single SDH VC-4-4C interface, or you can partition it into the following OC slices:
- SDH virtual concatenation 4 (VC-4) and channelized AU-4 interfaces (4 interfaces, any combination)
- Channelized T3 or T3 interfaces from a channelized AU-4 interface (3 interfaces, any combination)
- Channelized T1 or T1 interfaces from a channelized T3 interface (28 interfaces, any combination)
- NxDS0 interfaces from a channelized T1 interface
![]() | Note: If you configure the per-unit-scheduler statement on the physical interface of a 4-port channelized OC-12 IQ PIC and configure 975 logical interfaces or data link connection identifiers (DLCIs), some of the logical interfaces or DLCIs will drop all packets intermittently. |
This section describes how to configure the following channelized OC12 IQ interfaces on a Channelized OC12 IQ PIC configured in SDH mode:
- Configuring Channelized OC12/STM4 IQ PICs for SDH Mode
- Configuring an Unpartitioned SDH (VC-4-4C) Interface on a Channelized OC12/STM4 IQ PIC
- Configuring SDH (VC-4) Interfaces on Channelized OC12/STM4 IQ PICs
- Configuring Channelized AU-4 Interfaces
- Configuring T3 or Channelized T3 Interfaces Under Channelized AU-4 Interfaces
- Configuring T1 or Channelized T1 Interfaces Under Channelized AU-4 Interfaces
- Configuring T1 or Channelized T1 Interfaces Under Channelized T3 Interfaces
- Configuring NxDS0 Interfaces on Channelized OC12/STM4 IQ PICs
Configuring Channelized OC12/STM4 IQ PICs for SDH Mode
To configure a Channelized OC12 IQ PIC to operate in SDH mode, include the framing sdh statement at the [edit chassis fpc fpc/pic/port] hierarchy level:
This configuration creates interface cstm4-0/2/0.
For more information, see the Junos OS System Basics Configuration Guide.
Configuring an Unpartitioned SDH (VC-4-4C) Interface on a Channelized OC12/STM4 IQ PIC
On a Channelized OC12 IQ PIC, you can configure one SDH (VC-4-4C) interface. To configure an SDH (VC-4-4C) interface, include the no-partition and interface-type statements at the [edit interfaces cstm4-fpc/pic/port] hierarchy level:
This configuration creates interface so-fpc/pic/port.
Example: Configuring an Unpartitioned SDH (VC-4-4C) Interface
Configure an unpartitioned SDH (VC-4-4C) interface, using partition 1 and OC slices 4 through 6:
This configuration creates the interface so-0/2/0.
Configuring SDH (VC-4) Interfaces on Channelized OC12/STM4 IQ PICs
To configure an SDH (VC-4) interface on a Channelized OC12 IQ PIC, include the partition, oc-slice, and interface-type statements at the [edit interfaces cstm4-fpc/pic/port] hierarchy level, specifying the so interface type:
This configuration creates interface so-fpc/pic/port:channel.
The partition number is the sublevel interface partition index and is correlated with the channel number. For Channelized OC12 IQ PICs, the OC-slice range can be from 1 through 12.
![]() | Note: For channelized OC12 IQ interfaces, channel numbering begins with 1 (:1). |
The OC-slice range is the range of SONET/SDH slices. For SDH interfaces, the OC-slice range specifies the bandwidth size required for the interface type you are configuring. SDH (VC-4) interfaces must occupy three consecutive OC slices per interface, in one of the following forms:
- 1–3
- 4–6
- 7–9
- 10–12
The interface type is the channelized interface type or data channel you are creating.
Example: Configuring SDH (VC-4) Interfaces
Configure SDH (VC-4) interfaces:
This configuration creates the interfaces so-0/2/0:1 through so-0/2/0:4.
Configuring Channelized AU-4 Interfaces
To configure a channelized AU-4 interface, include the partition, oc-slice, and interface-type statements at the [edit interfaces cstm4-fpc/pic/port] hierarchy level, specifying the cau4 interface type:
This configuration creates interface cau4-fpc/pic/port:channel.
The partition number is the sublevel interface partition index. For SDH interfaces, the partition number is not correlated with bandwidth size. A channelized STM-4 interface can have from 1 through 4 partition numbers.
![]() | Note: For channelized OC12 interfaces, channel numbering begins with 0 (:0). For channelized OC12 interfaces (both IQ and IQE), channel numbering begins with 1 (:1). |
The OC-slice range is the range of SONET/SDH slices. For SDH interfaces, the OC-slice range specifies the bandwidth size required for the interface type you are configuring. Channelized AU-4 IQ interfaces must occupy three consecutive OC slices per interface, in one of the following forms:
- 1–3
- 4–6
- 7–9
- 10–12
The interface type is the channelized interface type or data channel you are creating.
Example: Configuring Channelized AU-4 Interfaces
Configure channelized AU-4 interfaces, using partitions 1 through 4:
This configuration creates the interfaces cau4-0/2/0:1 through cau4-0/2/0:4.
Configuring T3 or Channelized T3 Interfaces Under Channelized AU-4 Interfaces
To configure T3 or channelized T3 interfaces, include the partition and interface-type statements at the [edit interfaces cau4-fpc/pic/port] hierarchy level, specifying the t3 or ct3 interface type:
This configuration creates the interfaces t3-fpc/pic/port:channel and ct3-fpc/pic/port:channel.
![]() | Note: Class-of-service (CoS) rules cannot be applied to an individual channel configured on channelized IQ interfaces. You can apply CoS rules only to the aggregate bit streams. |
Example: Configuring T3 or Channelized T3 Interfaces
Configure T3 and channelized T3 interfaces, using partition 1 and partition 2:
Configuring T1 or Channelized T1 Interfaces Under Channelized AU-4 Interfaces
To configure T1 or channelized T1 interfaces under channelized AU-4 interfaces, include the partition and interface-type statements at the [edit interfaces cau4-fpc/pic/port] hierarchy level, specifying the t1 or ct1 interface type:
This configuration creates the interfaces t1-fpc/pic/port:channel and ct1-fpc/pic/port:channel.
![]() | Note: Class-of-service (CoS) rules cannot be applied to an individual channel configured on channelized IQ interfaces. You can apply CoS rules only to the aggregate bit streams. |
Example: Configuring T1 or Channelized T1 Interfaces Under Channelized AU-4 Interfaces
Configure T1 and channelized T1 interfaces, using partition 1 and partition 2:
Configuring T1 or Channelized T1 Interfaces Under Channelized T3 Interfaces
To configure T1 or channelized T1 interfaces under channelized T3 interfaces, include the partition and interface-type statements at the [edit interfaces ct3-fpc/pic/port] hierarchy level, specifying the t1 or ct1 interface type:
This configuration creates the interfaces t1-fpc/pic/port:channel and ct1-fpc/pic/port:channel.
![]() | Note: Class-of-service (CoS) rules cannot be applied to an individual channel configured on channelized IQ interfaces. You can apply CoS rules only to the aggregate bit streams. |
Example: Configuring T1 or Channelized T1 Interfaces Under Channelized T3 Interfaces
Configure T1 or channelized T1 interfaces, using partition 3 and partition 4:
This configuration creates interfaces t1-0/2/0:1:2:3 and ct1-0/2/0:1:2:4.
Configuring NxDS0 Interfaces on Channelized OC12/STM4 IQ PICs
Configure channelized NxDS0 IQ interfaces on the channelized T1 IQ interface by including the partition, timeslots, and interface-type statements at the [edit interfaces ct1-fpc/pic/port:channel] hierarchy level, specifying the ds interface type:
This configuration creates the interface ds-fpc/pic/port:channel.
The time-slot range is from 1 through 24. You can designate any combination of time slots. To configure ranges, use hyphens. To configure discontinuous time slots, use commas. You can use a combination of ranges and discontinuous time slots:
Example: Configuring NxDS0 Interfaces
Configure channelized NxDS0 interfaces, using partition 4 and time slots 1 through 10:
This configuration creates interface ds-0/2/0:1:2:3:4.