- play_arrow Overview
- play_arrow Global Navigation Satellite System (GNSS)
- play_arrow GPS Systems on Routing Platforms
- play_arrow Integrated GNSS on Routing Platforms
- play_arrow GNSS Configuration for Routers Using External GNSS Receiver
- play_arrow Assisted Partial Timing Support (APTS) on Routing Platforms
-
- play_arrow Network Time Protocol
- play_arrow NTP Concepts
- play_arrow NTP Configuration Examples
-
- play_arrow Synchronous Ethernet
- play_arrow Synchronous Ethernet Overview
- play_arrow Synchronous Ethernet on 10-Gigabit Ethernet MIC
-
- play_arrow Clock Synchronization
- play_arrow Clock Synchronization Concepts
- play_arrow Clock Synchronization for ACX Series Routers
- play_arrow Clock Synchronization for MX Series Routers
- play_arrow Clock Synchronization for PTX Series Routers
- play_arrow Centralized Clocking
-
- play_arrow Hybrid Mode
- play_arrow Hybrid Mode Overview
- play_arrow Hybrid Mode and ESMC Quality-Level Mapping
- Configure Hybrid Mode and ESMC Quality-Level Mapping Overview
- Configure Hybrid Mode with Mapping of the PTP Clock Class to the ESMC Quality-Level
- Configure Hybrid Mode with a User-Defined Mapping of the PTP Clock Class to the ESMC Quality-Level
- Example: Configure Hybrid Mode and ESMC Quality-Level Mapping on ACX Series Router
- Example: Configure Hybrid Mode and ESMC Quality-Level Mapping on MX240 Router
-
- play_arrow Configuration Statements and Operational Commands
- play_arrow Appendix
PHY Timestamping
The PHY timestamping refers to the timestamping of the IEEE 1588 event packets at the 1-Gigabit Ethernet and 10-Gigabit Ethernet PHY. Timestamping the packet in the PHY results in higher stability of recovered clock.
Juniper Networks recommends that you configure timestamping at the physical layer if the port supports IEEE 1588 timestamping.
The PHY timestamping on ACX updates the correction field of the packet. ACX supports PHY timestamping in ordinary clock and boundary clock modes.
On 10-Gigabit Ethernet ports, PHY timestamping and WAN-PHY framing are mutually exclusive—that is, you cannot configure PHY timestamping on a 10-Gigabit Ethernet port if you have configured WAN-PHY framing mode on that port. This is applicable only for MPC5E and MPC6E with 24x10XGE MIC. PHY timestamping is not supported on the enhanced MPCs MPC1E, MPC2E, and MPC4E. Only hardware timestamping is supported on these MPCs. Therefore, a packet delay variation (also known as jitter) of up to 1 microsecond is observed on these MPCs for a very small percentage of packets occasionally. Hardware timestamping is typically timestamping either at FPGA or similar device.
On Junos Evo platforms, PHY timestamping is enabled by
default and the phy-timestamping configuration option is unavailable.
