- play_arrow Overview
- play_arrow Understanding How Class of Service Manages Congestion and Defines Traffic Forwarding Behavior
- Understanding How Class of Service Manages Congestion and Controls Service Levels in the Network
- How CoS Applies to Packet Flow Across a Network
- The Junos OS CoS Components Used to Manage Congestion and Control Service Levels
- Mapping CoS Component Inputs to Outputs
- Default Junos OS CoS Settings
- Packet Flow Through the Junos OS CoS Process Overview
- Configuring Basic Packet Flow Through the Junos OS CoS Process
- Example: Classifying All Traffic from a Remote Device by Configuring Fixed Interface-Based Classification
- Interface Types That Do Not Support Junos OS CoS
-
- play_arrow Configuring Platform-Specific Functionality
- play_arrow Configuring Class of Service on ACX Series Universal Metro Routers
- CoS on ACX Series Routers Features Overview
- Understanding CoS CLI Configuration Statements on ACX Series Routers
- DSCP Propagation and Default CoS on ACX Series Routers
- Configuring CoS on ACX Series Routers
- Classifiers and Rewrite Rules at the Global, Physical, and Logical Interface Levels Overview
- Configuring Classifiers and Rewrite Rules at the Global and Physical Interface Levels
- Applying DSCP and DSCP IPv6 Classifiers on ACX Series Routers
- Schedulers Overview for ACX Series Routers
- Shared and Dedicated Buffer Memory Pools on ACX Series Routers
- CoS for PPP and MLPPP Interfaces on ACX Series Routers
- CoS for NAT Services on ACX Series Routers
- Hierarchical Class of Service in ACX Series Routers
- Storm Control on ACX Series Routers Overview
- play_arrow Configuring Class of Service on MX Series 5G Universal Routing Platforms
- Junos CoS on MX Series 5G Universal Routing Platforms Overview
- CoS Features and Limitations on MX Series Routers
- Configuring and Applying IEEE 802.1ad Classifiers
- Scheduling and Shaping in Hierarchical CoS Queues for Traffic Routed to GRE Tunnels
- Example: Performing Output Scheduling and Shaping in Hierarchical CoS Queues for Traffic Routed to GRE Tunnels
- CoS-Based Interface Counters for IPv4 or IPv6 Aggregate on Layer 2
- Enabling a Timestamp for Ingress and Egress Queue Packets
- play_arrow Configuring Class of Service on PTX Series Packet Transport Routers
- CoS Features and Limitations on PTX Series Routers
- CoS Feature Differences Between PTX Series Packet Transport Routers and T Series Routers
- Understanding Scheduling on PTX Series Routers
- Virtual Output Queues on PTX Series Packet Transport Routers
- Example: Configuring Excess Rate for PTX Series Packet Transport Routers
- Identifying the Source of RED Dropped Packets on PTX Series Routers
- Configuring Queuing and Shaping on Logical Interfaces on PTX Series Routers
- Example: Configuring Queuing and Shaping on Logical Interfaces in PTX Series Packet Transport Routers
- Example: Configuring Strict-Priority Scheduling on a PTX Series Router
- CoS Support on EVPN VXLANs
- Understanding CoS CLI Configuration Statements on PTX Series Routers
- Classification Based on Outer Header of Decapsulation Tunnel
-
- play_arrow Configuring Line Card-Specific and Interface-Specific Functionality
- play_arrow Feature Support of Line Cards and Interfaces
- play_arrow Configuring Class of Service for Tunnels
- play_arrow Configuring Class of Service on Services PICs
- CoS on Services PICs Overview
- Configuring CoS Rules on Services PICs
- Configuring CoS Rule Sets on Services PICs
- Example: Configuring CoS Rules on Services PICs
- Packet Rewriting on Services Interfaces
- Multiservices PIC ToS Translation
- Fragmentation by Forwarding Class Overview
- Configuring Fragmentation by Forwarding Class
- Configuring Drop Timeout Interval for Fragmentation by Forwarding Class
- Example: Configuring Fragmentation by Forwarding Class
- Allocating Excess Bandwidth Among Frame Relay DLCIs on Multiservices PICs
- Configuring Rate Limiting and Sharing of Excess Bandwidth on Multiservices PICs
- play_arrow Configuring Class of Service on IQ and Enhanced IQ (IQE) PICs
- CoS on Enhanced IQ PICs Overview
- Calculation of Expected Traffic on IQE PIC Queues
- Configuring the Junos OS to Support Eight Queues on IQ Interfaces for T Series and M320 Routers
- BA Classifiers and ToS Translation Tables
- Configuring ToS Translation Tables
- Configuring Hierarchical Layer 2 Policers on IQE PICs
- Configuring Excess Bandwidth Sharing on IQE PICs
- Configuring Rate-Limiting Policers for High Priority Low-Latency Queues on IQE PICs
- Applying Scheduler Maps and Shaping Rate to Physical Interfaces on IQ PICs
- Applying Scheduler Maps to Chassis-Level Queues
- play_arrow Configuring Class of Service on Ethernet IQ2 and Enhanced IQ2 PICs
- CoS on Enhanced IQ2 PICs Overview
- CoS Features and Limitations on IQ2 and IQ2E PICs (M Series and T Series)
- Differences Between Gigabit Ethernet IQ and Gigabit Ethernet IQ2 PICs
- Shaping Granularity Values for Enhanced Queuing Hardware
- Ethernet IQ2 PIC RTT Delay Buffer Values
- Configuring BA Classifiers for Bridged Ethernet
- Setting the Number of Egress Queues on IQ2 and Enhanced IQ2 PICs
- Configuring the Number of Schedulers per Port for Ethernet IQ2 PICs
- Applying Scheduler Maps to Chassis-Level Queues
- CoS for L2TP Tunnels on Ethernet Interface Overview
- Configuring CoS for L2TP Tunnels on Ethernet Interfaces
- Configuring LNS CoS for Link Redundancy
- Example: Configuring L2TP LNS CoS Support for Link Redundancy
- Configuring Shaping on 10-Gigabit Ethernet IQ2 PICs
- Configuring Per-Unit Scheduling for GRE Tunnels Using IQ2 and IQ2E PICs
- Understanding Burst Size Configuration on IQ2 and IQ2E Interfaces
- Configuring Burst Size for Shapers on IQ2 and IQ2E Interfaces
- Configuring a CIR and a PIR on Ethernet IQ2 Interfaces
- Example: Configuring Shared Resources on Ethernet IQ2 Interfaces
- Configuring and Applying IEEE 802.1ad Classifiers
- Configuring Rate Limits to Protect Lower Queues on IQ2 and Enhanced IQ2 PICs
- Simple Filters Overview
- Configuring a Simple Filter
- play_arrow Configuring Class of Service on 10-Gigabit Ethernet LAN/WAN PICs with SFP+
- CoS on 10-Gigabit Ethernet LAN/WAN PIC with SFP+ Overview
- BA and Fixed Classification on 10-Gigabit Ethernet LAN/WAN PIC with SFP+ Overview
- DSCP Rewrite for the 10-Gigabit Ethernet LAN/WAN PIC with SFP+
- Configuring DSCP Rewrite for the 10-Gigabit Ethernet LAN/WAN PIC
- Queuing on 10-Gigabit Ethernet LAN/WAN PICs Properties
- Mapping Forwarding Classes to CoS Queues on 10-Gigabit Ethernet LAN/WAN PICs
- Scheduling and Shaping on 10-Gigabit Ethernet LAN/WAN PICs Overview
- Example: Configuring Shaping Overhead on 10-Gigabit Ethernet LAN/WAN PICs
- play_arrow Configuring Class of Service on Enhanced Queuing DPCs
- Enhanced Queuing DPC CoS Properties
- Configuring Rate Limits on Enhanced Queuing DPCs
- Configuring WRED on Enhanced Queuing DPCs
- Configuring MDRR on Enhanced Queuing DPCs
- Configuring Excess Bandwidth Sharing
- Configuring Customer VLAN (Level 3) Shaping on Enhanced Queuing DPCs
- Simple Filters Overview
- Configuring Simple Filters on Enhanced Queuing DPCs
- Configuring a Simple Filter
- play_arrow Configuring Class of Service on MICs, MPCs, and MLCs
- CoS Features and Limitations on MIC and MPC Interfaces
- Dedicated Queue Scaling for CoS Configurations on MIC and MPC Interfaces Overview
- Verifying the Number of Dedicated Queues Configured on MIC and MPC Interfaces
- Scaling of Per-VLAN Queuing on Non-Queuing MPCs
- Increasing Available Bandwidth on Rich-Queuing MPCs by Bypassing the Queuing Chip
- Flexible Queuing Mode
- Multifield Classifier for Ingress Queuing on MX Series Routers with MPC
- Example: Configuring a Filter for Use as an Ingress Queuing Filter
- Ingress Queuing Filter with Policing Functionality
- Ingress Rate Limiting on MX Series Routers with MPCs
- Rate Shaping on MIC and MPC Interfaces
- Per-Priority Shaping on MIC and MPC Interfaces Overview
- Example: Configuring Per-Priority Shaping on MIC and MPC Interfaces
- Configuring Static Shaping Parameters to Account for Overhead in Downstream Traffic Rates
- Example: Configuring Static Shaping Parameters to Account for Overhead in Downstream Traffic Rates
- Traffic Burst Management on MIC and MPC Interfaces Overview
- Understanding Hierarchical Scheduling for MIC and MPC Interfaces
- Configuring Ingress Hierarchical CoS on MIC and MPC Interfaces
- Configuring a CoS Scheduling Policy on Logical Tunnel Interfaces
- Per-Unit Scheduling and Hierarchical Scheduling for MPC Interfaces
- Managing Dedicated and Remaining Queues for Static CoS Configurations on MIC and MPC Interfaces
- Excess Bandwidth Distribution on MIC and MPC Interfaces Overview
- Bandwidth Management for Downstream Traffic in Edge Networks Overview
- Scheduler Delay Buffering on MIC and MPC Interfaces
- Managing Excess Bandwidth Distribution on Static Interfaces on MICs and MPCs
- Drop Profiles on MIC and MPC Interfaces
- Intelligent Oversubscription on MIC and MPC Interfaces Overview
- Jitter Reduction in Hierarchical CoS Queues
- Example: Reducing Jitter in Hierarchical CoS Queues
- CoS on Ethernet Pseudowires in Universal Edge Networks Overview
- CoS Scheduling Policy on Logical Tunnel Interfaces Overview
- Configuring CoS on an Ethernet Pseudowire for Multiservice Edge Networks
- CoS for L2TP LNS Inline Services Overview
- Configuring Static CoS for an L2TP LNS Inline Service
- CoS on Circuit Emulation ATM MICs Overview
- Configuring CoS on Circuit Emulation ATM MICs
- Understanding IEEE 802.1p Inheritance push and swap from a Transparent Tag
- Configuring IEEE 802.1p Inheritance push and swap from the Transparent Tag
- CoS on Application Services Modular Line Card Overview
- play_arrow Configuring Class of Service on Aggregated, Channelized, and Gigabit Ethernet Interfaces
- Limitations on CoS for Aggregated Interfaces
- Policer Support for Aggregated Ethernet Interfaces Overview
- Understanding Schedulers on Aggregated Interfaces
- Examples: Configuring CoS on Aggregated Interfaces
- Hierarchical Schedulers on Aggregated Ethernet Interfaces Overview
- Configuring Hierarchical Schedulers on Aggregated Ethernet Interfaces
- Example: Configuring Scheduling Modes on Aggregated Interfaces
- Enabling VLAN Shaping and Scheduling on Aggregated Interfaces
- Class of Service on demux Interfaces
- Example: Configuring Per-Unit Schedulers for Channelized Interfaces
- Applying Layer 2 Policers to Gigabit Ethernet Interfaces
-
- play_arrow Configuration Statements and Operational Commands
Applying Scheduler Maps and Shaping Rate to DLCIs and VLANs
By default, output scheduling is not enabled on logical interfaces. Logical interfaces without shaping configured share a default scheduler. This scheduler has a committed information rate (CIR) that equals 0. (The CIR is the guaranteed rate.) The default scheduler has a peak information rate (PIR) that equals the physical interface shaping rate.
If you apply a shaping rate, you must keep in mind that the transit statistics for physical interfaces are obtained from the packet forwarding engine, but the traffic statistics are supplied by the PIC. Therefore, if shaping is applied to the PIC, the count of packets in the transit statistics fields do not always agree with the counts in the traffic statistics. For example, the IPv6 transit statistics will not necessarily match the traffic statistics on the interface. However, at the logical interface (DLCI) level, both transit and traffic statistics are obtained from the Packet Forwarding Engine and will not show any difference.
Logical interface scheduling (also called per-unit scheduling) allows you to enable multiple output queues on a logical interface and associate customized output scheduling and shaping for each queue.
Ingress scheduling does not support logical interface scheduling.
You can configure logical interface scheduling on the following PICs:
Multiservices and Services PICs , on link services IQ (
lsq-
) interfacesChannelized E1 IQ PIC
Channelized OC3 IQ PIC
Channelized OC12 IQ PIC (Per-unit scheduling is not supported on T1 interfaces configured on this PIC.)
Channelized STM1 IQ PIC
Channelized T3 IQ PIC
E3 IQ PIC
Gigabit Ethernet IQ PIC
Gigabit Ethernet IQ2 PIC
IQE PICs
You can configure logical interface scheduling on the following MICs and MPCs as well as any MPC that contains a queuing chip:
16x10GE MPC
MPC3E:
2x10GE MIC with XFP
10x10GE MIC with SFP+
2x40GE MIC with QSFP+
1x100GE MIC with CXP
MPC4E:
32x10GE with SFPP
2x100GE + 8x10GE with SFPP
MPC6E:
24x10GE MIC with SFPP
24x10GE MIC with SFPP OTN
2x100GE MIC with CFP2 OTN
4x100GE MIC with CXP
For Channelized and Gigabit Ethernet IQ PICs only, you can configure
a shaping rate for a VLAN or DLCI and oversubscribe the physical interface
by including the shaping-rate
statement at the [edit
class-of-service traffic-control-profiles]
hierarchy level.
With this configuration approach, you can independently control the
delay-buffer rate, as described in Oversubscribing
Interface Bandwidth.
Physical interfaces (for example, t3-0/0/0
, t3-0/0/0:0
, and ge-0/0/0
) support scheduling with
any encapsulation type pertinent to that physical interface. For a
single port, you cannot apply scheduling to the physical interface
if you apply scheduling to one or more of the associated logical interfaces.
For Gigabit Ethernet IQ2 PIC PICs only, you can configure hierarchical traffic shaping, meaning the shaping is performed on both the physical interface and the logical interface. You can also configure input traffic scheduling and shared scheduling. For more information, see CoS on Enhanced IQ2 PICs Overview.
Logical interfaces (for example. t3-0/0/0.0
, ge-0/0/0.0
, and t1-0/0/0:0.1
) support scheduling
on DLCIs or VLANs only. Furthermore, logical interface scheduling
is not supported on PICs that do not have IQ.
In the Junos OS implementation, the term logical
interfaces generally refers to interfaces you configure
by including the unit
statement at the [edit interfaces interface-name]
hierarchy level. As such, logical
interfaces have the logical
descriptor
at the end of the interface name, as in ge-0/0/0.1
or t1-0/0/0:0.1
, where the logical unit number is 1
.
Although channelized interfaces are generally thought of as
logical or virtual, the Junos OS sees T3, T1, and NxDS0 interfaces within a channelized IQ PIC as physical interfaces.
For example, both t3-0/0/0
and t3-0/0/0:1
are
treated as physical interfaces by the Junos OS. In contrast, t3-0/0/0.2
and t3-0/0/0:1.2
are considered logical
interfaces because they have the .2
at the end of the interface
names.
Within the [edit class-of-service]
hierarchy level,
you cannot use the .logical
descriptor
when you assign properties to logical interfaces. Instead, you must
include the unit
statement in the configuration. For example:
[edit class-of-service] user@host# set interfaces t3-0/0/0 unit 0 scheduler-map map1
Table 1 shows the interfaces/PICs that support fine-grained queuing and scheduling.
Interface Type | PIC Type | Supported | Example Configuration |
---|---|---|---|
IQ PICs | |||
Physical interfaces | ATM2 IQ | Yes | Example of supported configuration: [edit class-of-service interfaces at-0/0/0] scheduler-map map-1; |
Channelized interfaces configured on IQ PICs | Channelized DS3 IQ | Yes | Example of supported configuration: [edit class-of-service interfaces t1-0/0/0:1] scheduler-map map-1; |
Logical interfaces (DLCIs and VLANs only) configured on IQ PICs | Gigabit Ethernet IQ with VLAN tagging enabled | Yes | Example of supported configuration: [edit class-of-service interfaces ge-0/0/0 unit 1] scheduler-map map-1; |
E3 IQ with Frame Relay encapsulation | Yes | Example of supported configuration: [edit class-of-service interfaces e3-0/0/0 unit 1] scheduler-map map-1; | |
Channelized OC3 IQ with Frame Relay encapsulation | Yes | Example of supported configuration: [edit class-of-service interfaces t1-1/0/0:1:1 unit 0] scheduler-map map-1; | |
Channelized STM1 IQ with Frame Relay encapsulation | Yes | Example of supported configuration: [edit class-of-service interfaces e1-0/0/0:1 unit 1] scheduler-map map-1; | |
Channelized T3 IQ with Frame Relay encapsulation | Yes | Example of supported configuration: [edit class-of-service interfaces t1-0/0/0 unit 1] scheduler-map map-1; | |
Logical interfaces configured on IQ PICs (interfaces that are not DLCIs or VLANs) | E3 IQ PIC with Cisco HDLC encapsulation | No | No |
ATM2 IQ PIC with LLC/SNAP encapsulation | No | No | |
Channelized OC12 IQ PIC with PPP encapsulation | No | No | |
Non-IQ PICs | |||
Physical interfaces | T3 | Yes | Example of supported configuration: [edit class-of-service interfaces t3-0/0/0] scheduler-map map-1; |
Channelized OC12 PIC | Channelized OC12 | Yes | Example of supported configuration: [edit class-of-service interfaces t3-0/0/0:1] scheduler-map map-1; |
Channelized interfaces (except the Channelized OC12 PIC) | Channelized STM1 | No | No |
Logical interfaces | Fast Ethernet | No | No |
Gigabit Ethernet | No | No | |
ATM1 | No | No | |
Channelized OC12 | No | No |
Table 2 shows the MICs and MPCs that support fine-grained queuing and scheduling.
MPC | MIC | Supported | Example Configuration |
---|---|---|---|
Fixed Configuration MPCs | |||
16x10GE MPC | No | Yes | [edit class-of-service interfaces ge-0/0/0 unit 1] scheduler-map map-1; |
32x10GE MPC4E | No | Yes | [edit class-of-service interfaces ge-0/0/0 unit 1] scheduler-map map-1; |
2x100GE + 8x10GE MPC4E | No | Yes | [edit class-of-service interfaces ge-0/0/0 unit 1] scheduler-map map-1; |
6x40GE + 24x10GE MPC5E | No | No | No |
6x40GE + 24x10GE MPC5EQ | No | Yes | [edit class-of-service interfaces ge-0/0/0 unit 1] scheduler-map map-1; |
2x100GE + 4x10GE MPC5E | No | No | No |
2x100GE + 4x10GE MPC5EQ | No | Yes | [edit class-of-service interfaces ge-0/0/0 unit 1] scheduler-map map-1; |
MPCs | |||
MPC1 | No | No | No |
MPC1E | No | No | No |
MPC1 Q | Any supported MIC | Yes | Example of supported configuration: [edit class-of-service interfaces ge-0/0/0 unit 1] scheduler-map map-1; |
MPC1E Q | Any supported MIC | Yes | Example of supported configuration: [edit class-of-service interfaces ge-0/0/0 unit 1] scheduler-map map-1; |
MPC2 | No | No | No |
MPC2E | No | No | No |
MPC2 Q | Any supported MIC | Yes | Example of supported configuration: [edit class-of-service interfaces ge-0/0/0 unit 1] scheduler-map map-1; |
MPC2E Q | Any supported MIC | Yes | Example of supported configuration: [edit class-of-service interfaces ge-0/0/0 unit 1] scheduler-map map-1; |
MPC2 EQ | Any supported MIC | Yes | Example of supported configuration: [edit class-of-service interfaces ge-0/0/0 unit 1] scheduler-map map-1; |
MPC2E EQ | Any supported MIC | Yes | Example of supported configuration: [edit class-of-service interfaces ge-0/0/0 unit 1] scheduler-map map-1; |
MPC2E P | No | No | No |
MPC3E | 10-Gigabit Ethernet MIC with SFP+ | Yes | Example of supported configuration: [edit class-of-service interfaces xe-0/0/0 unit 1] scheduler-map map-1; |
40-Gigabit Ethernet MIC with QSFP+ | Yes | Example of supported configuration: [edit class-of-service interfaces et-0/0/0 unit 1] scheduler-map map-1; | |
100-Gigabit Ethernet MIC with CXP | Yes | Example of supported configuration: [edit class-of-service interfaces et-0/0/0 unit 1] scheduler-map map-1; | |
MPC6E | Any supported MIC | Yes | Example of supported configuration: [edit class-of-service interfaces et-0/0/0 unit 1] scheduler-map map-1; |
To configure scheduling on logical interfaces:
Enable per-unit scheduling on the interface by including the
per-unit-scheduler
statement at the[edit interfaces interface-name]
hierarchy level:content_copy zoom_out_map[edit interfaces interface-name] per-unit-scheduler;
When including the
per-unit-scheduler
statement, you must also include thevlan-tagging
statement or theflexible-vlan-tagging
statement (to apply scheduling to VLANs) or theencapsulation frame-relay
statement (to apply scheduling to DLCIs) at the[edit interfaces interface-name]
hierarchy level.When you include this statement, the maximum number of VLANs supported is 768 on a single-port Gigabit Ethernet IQ PIC. On a dual-port Gigabit Ethernet IQ PIC, the maximum number is 384.
See Scaling of Per-VLAN Queuing on Non-Queuing MPCs for scaling information on non-queuing MPCs.
Associate a scheduler with the interface by including the
scheduler-map
statement at the[edit class-of-service interfaces interface-name unit logical-unit-number]
hierarchy level:content_copy zoom_out_map[edit class-of-service interfaces interface-name unit logical-unit-number] scheduler-map map-name;
Alternatively, associate a scheduler with the interface by including the
scheduler-map
statement at the[edit class-of-service traffic-control-profiles traffic control profile name]
hierarchy level and then include theoutput-traffic-control-profile
statement at the[edit class-of-service interfaces interface name unit logical unit number]
hierarchy level.content_copy zoom_out_map[edit class-of-service traffic-control-profiles traffic control profile name] scheduler-map map-name;
content_copy zoom_out_map[edit class-of-service interfaces interface-name unit logical-unit-number] output-traffic-control-profile traffic-control-profile-name;
Configure shaping on the interface by including the
shaping-rate
statement at the[edit class-of-service interfaces interface-name unit logical-unit-number]
hierarchy level:content_copy zoom_out_map[edit class-of-service interfaces interface-name unit logical-unit-number] shaping-rate rate;
Note:You can also apply the shaping rate to the traffic control profile.
By default, the logical interface bandwidth is the average of unused bandwidth for the number of logical interfaces that require default bandwidth treatment. You can specify a peak bandwidth rate in bps, either as a complete decimal number or as a decimal number followed by the abbreviation
k
(1000),m
(1,000,000), org
(1,000,000,000). The range is from 1000 through 6,400,000,000,000 bps. For the IQ2 Gigabit Ethernet PIC, the minimum is 80,000 bps, and for the IQ2 10 Gigabit Ethernet PIC, the minimum is 160,000 bps. For the 16x10GE MPC, the minimum is 250,000 bps, and for the MPC3E, MPC4E, and MPC6E, the minimum is 292,000 bps.For FRF.16 bundles on link services interfaces, only shaping rates based on percentage are supported.