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Applying Scheduler Maps and Shaping Rate to DLCIs and VLANs

By default, output scheduling is not enabled on logical interfaces. Logical interfaces without shaping configured share a default scheduler. This scheduler has a committed information rate (CIR) that equals 0. (The CIR is the guaranteed rate.) The default scheduler has a peak information rate (PIR) that equals the physical interface shaping rate.

Note:

If you apply a shaping rate, you must keep in mind that the transit statistics for physical interfaces are obtained from the packet forwarding engine, but the traffic statistics are supplied by the PIC. Therefore, if shaping is applied to the PIC, the count of packets in the transit statistics fields do not always agree with the counts in the traffic statistics. For example, the IPv6 transit statistics will not necessarily match the traffic statistics on the interface. However, at the logical interface (DLCI) level, both transit and traffic statistics are obtained from the Packet Forwarding Engine and will not show any difference.

Logical interface scheduling (also called per-unit scheduling) allows you to enable multiple output queues on a logical interface and associate customized output scheduling and shaping for each queue.

Note:

Ingress scheduling does not support logical interface scheduling.

You can configure logical interface scheduling on the following PICs:

  • Multiservices and Services PICs , on link services IQ (lsq-) interfaces

  • Channelized E1 IQ PIC

  • Channelized OC3 IQ PIC

  • Channelized OC12 IQ PIC (Per-unit scheduling is not supported on T1 interfaces configured on this PIC.)

  • Channelized STM1 IQ PIC

  • Channelized T3 IQ PIC

  • E3 IQ PIC

  • Gigabit Ethernet IQ PIC

  • Gigabit Ethernet IQ2 PIC

  • IQE PICs

You can configure logical interface scheduling on the following MICs and MPCs as well as any MPC that contains a queuing chip:

  • 16x10GE MPC

  • MPC3E:

    • 2x10GE MIC with XFP

    • 10x10GE MIC with SFP+

    • 2x40GE MIC with QSFP+

    • 1x100GE MIC with CXP

  • MPC4E:

    • 32x10GE with SFPP

    • 2x100GE + 8x10GE with SFPP

  • MPC6E:

    • 24x10GE MIC with SFPP

    • 24x10GE MIC with SFPP OTN

    • 2x100GE MIC with CFP2 OTN

    • 4x100GE MIC with CXP

For Channelized and Gigabit Ethernet IQ PICs only, you can configure a shaping rate for a VLAN or DLCI and oversubscribe the physical interface by including the shaping-rate statement at the [edit class-of-service traffic-control-profiles] hierarchy level. With this configuration approach, you can independently control the delay-buffer rate, as described in Oversubscribing Interface Bandwidth.

Physical interfaces (for example, t3-0/0/0, t3-0/0/0:0, and ge-0/0/0) support scheduling with any encapsulation type pertinent to that physical interface. For a single port, you cannot apply scheduling to the physical interface if you apply scheduling to one or more of the associated logical interfaces.

For Gigabit Ethernet IQ2 PIC PICs only, you can configure hierarchical traffic shaping, meaning the shaping is performed on both the physical interface and the logical interface. You can also configure input traffic scheduling and shared scheduling. For more information, see CoS on Enhanced IQ2 PICs Overview.

Logical interfaces (for example. t3-0/0/0.0, ge-0/0/0.0, and t1-0/0/0:0.1) support scheduling on DLCIs or VLANs only. Furthermore, logical interface scheduling is not supported on PICs that do not have IQ.

Note:

In the Junos OS implementation, the term logical interfaces generally refers to interfaces you configure by including the unit statement at the [edit interfaces interface-name] hierarchy level. As such, logical interfaces have the logical descriptor at the end of the interface name, as in ge-0/0/0.1 or t1-0/0/0:0.1, where the logical unit number is 1.

Although channelized interfaces are generally thought of as logical or virtual, the Junos OS sees T3, T1, and NxDS0 interfaces within a channelized IQ PIC as physical interfaces. For example, both t3-0/0/0 and t3-0/0/0:1 are treated as physical interfaces by the Junos OS. In contrast, t3-0/0/0.2 and t3-0/0/0:1.2 are considered logical interfaces because they have the .2 at the end of the interface names.

Within the [edit class-of-service] hierarchy level, you cannot use the .logical descriptor when you assign properties to logical interfaces. Instead, you must include the unit statement in the configuration. For example:

Table 1 shows the interfaces/PICs that support fine-grained queuing and scheduling.

Table 1: Fine-Grained Queuing and Scheduling Support by Interface or PIC Type

Interface Type

PIC Type

Supported

Example Configuration
IQ PICs

Physical interfaces

ATM2 IQ

Yes

Example of supported configuration:

[edit class-of-service interfaces at-0/0/0]
scheduler-map map-1;

Channelized interfaces configured on IQ PICs

Channelized DS3 IQ

Yes

Example of supported configuration:

[edit class-of-service interfaces t1-0/0/0:1]
scheduler-map map-1;

Logical interfaces (DLCIs and VLANs only) configured on IQ PICs

Gigabit Ethernet IQ with VLAN tagging enabled

Yes

Example of supported configuration:

[edit class-of-service interfaces ge-0/0/0 unit 1]
scheduler-map map-1;

E3 IQ with Frame Relay encapsulation

Yes

Example of supported configuration:

[edit class-of-service interfaces e3-0/0/0 unit 1]
scheduler-map map-1;

Channelized OC3 IQ with Frame Relay encapsulation

Yes

Example of supported configuration:

[edit class-of-service interfaces t1-1/0/0:1:1 unit 0]
scheduler-map map-1;

Channelized STM1 IQ with Frame Relay encapsulation

Yes

Example of supported configuration:

[edit class-of-service interfaces e1-0/0/0:1 unit 1]
scheduler-map map-1;

Channelized T3 IQ with Frame Relay encapsulation

Yes

Example of supported configuration:

[edit class-of-service interfaces t1-0/0/0 unit 1]
scheduler-map map-1;

Logical interfaces configured on IQ PICs (interfaces that are not DLCIs or VLANs)

E3 IQ PIC with Cisco HDLC encapsulation

No

No

ATM2 IQ PIC with LLC/SNAP encapsulation

No

No

Channelized OC12 IQ PIC with PPP encapsulation

No

No
Non-IQ PICs

Physical interfaces

T3

Yes

Example of supported configuration:

[edit class-of-service interfaces t3-0/0/0]
scheduler-map map-1;

Channelized OC12 PIC

Channelized OC12

Yes

Example of supported configuration:

[edit class-of-service interfaces t3-0/0/0:1]
scheduler-map map-1;

Channelized interfaces (except the Channelized OC12 PIC)

Channelized STM1

No

No

Logical interfaces

Fast Ethernet

No

No

Gigabit Ethernet

No

No

ATM1

No

No

Channelized OC12

No

No

Table 2 shows the MICs and MPCs that support fine-grained queuing and scheduling.

Table 2: Fine-Grained Queuing and Scheduling Support by MIC or MPC Type

MPC

MIC

Supported

Example Configuration
Fixed Configuration MPCs

16x10GE MPC

No

Yes

 
[edit class-of-service interfaces ge-0/0/0 unit 1]
scheduler-map map-1;

32x10GE MPC4E

No

Yes

 
[edit class-of-service interfaces ge-0/0/0 unit 1]
scheduler-map map-1;

2x100GE + 8x10GE MPC4E

No

Yes

 
[edit class-of-service interfaces ge-0/0/0 unit 1]
scheduler-map map-1;

6x40GE + 24x10GE MPC5E

No

No

No

6x40GE + 24x10GE MPC5EQ

No

Yes

 
[edit class-of-service interfaces ge-0/0/0 unit 1]
scheduler-map map-1;

2x100GE + 4x10GE MPC5E

No

No

No

2x100GE + 4x10GE MPC5EQ

No

Yes

 
[edit class-of-service interfaces ge-0/0/0 unit 1]
scheduler-map map-1;
MPCs

MPC1

No

No

No

MPC1E

No

No

No

MPC1 Q

Any supported MIC

Yes

Example of supported configuration:

[edit class-of-service interfaces ge-0/0/0 unit 1]
scheduler-map map-1;

MPC1E Q

Any supported MIC

Yes

Example of supported configuration:

[edit class-of-service interfaces ge-0/0/0 unit 1]
scheduler-map map-1;

MPC2

No

No

No

MPC2E

No

No

No

MPC2 Q

Any supported MIC

Yes

Example of supported configuration:

[edit class-of-service interfaces ge-0/0/0 unit 1]
scheduler-map map-1;

MPC2E Q

Any supported MIC

Yes

Example of supported configuration:

[edit class-of-service interfaces ge-0/0/0 unit 1]
scheduler-map map-1;

MPC2 EQ

Any supported MIC

Yes

Example of supported configuration:

[edit class-of-service interfaces ge-0/0/0 unit 1]
scheduler-map map-1;

MPC2E EQ

Any supported MIC

Yes

Example of supported configuration:

[edit class-of-service interfaces ge-0/0/0 unit 1]
scheduler-map map-1;

MPC2E P

No

No

No

MPC3E

10-Gigabit Ethernet MIC with SFP+

Yes

Example of supported configuration:

[edit class-of-service interfaces xe-0/0/0 unit 1]
scheduler-map map-1;

40-Gigabit Ethernet MIC with QSFP+

Yes

Example of supported configuration:

[edit class-of-service interfaces et-0/0/0 unit 1]
scheduler-map map-1;

100-Gigabit Ethernet MIC with CXP

Yes

Example of supported configuration:

[edit class-of-service interfaces et-0/0/0 unit 1]
scheduler-map map-1;

MPC6E

Any supported MIC

Yes

Example of supported configuration:

[edit class-of-service interfaces et-0/0/0 unit 1]
scheduler-map map-1;

To configure scheduling on logical interfaces:

  1. Enable per-unit scheduling on the interface by including the per-unit-scheduler statement at the [edit interfaces interface-name] hierarchy level:

    When including the per-unit-scheduler statement, you must also include the vlan-tagging statement or the flexible-vlan-tagging statement (to apply scheduling to VLANs) or the encapsulation frame-relay statement (to apply scheduling to DLCIs) at the [edit interfaces interface-name] hierarchy level.

    When you include this statement, the maximum number of VLANs supported is 768 on a single-port Gigabit Ethernet IQ PIC. On a dual-port Gigabit Ethernet IQ PIC, the maximum number is 384.

    See Scaling of Per-VLAN Queuing on Non-Queuing MPCs for scaling information on non-queuing MPCs.

  2. Associate a scheduler with the interface by including the scheduler-map statement at the [edit class-of-service interfaces interface-name unit logical-unit-number] hierarchy level:

    Alternatively, associate a scheduler with the interface by including the scheduler-map statement at the [edit class-of-service traffic-control-profiles traffic control profile name] hierarchy level and then include the output-traffic-control-profile statement at the [edit class-of-service interfaces interface name unit logical unit number] hierarchy level.

  3. Configure shaping on the interface by including the shaping-rate statement at the [edit class-of-service interfaces interface-name unit logical-unit-number] hierarchy level:

    Note:

    You can also apply the shaping rate to the traffic control profile.

    By default, the logical interface bandwidth is the average of unused bandwidth for the number of logical interfaces that require default bandwidth treatment. You can specify a peak bandwidth rate in bps, either as a complete decimal number or as a decimal number followed by the abbreviation k (1000), m (1,000,000), or g (1,000,000,000). The range is from 1000 through 6,400,000,000,000 bps. For the IQ2 Gigabit Ethernet PIC, the minimum is 80,000 bps, and for the IQ2 10 Gigabit Ethernet PIC, the minimum is 160,000 bps. For the 16x10GE MPC, the minimum is 250,000 bps, and for the MPC3E, MPC4E, and MPC6E, the minimum is 292,000 bps.

    For FRF.16 bundles on link services interfaces, only shaping rates based on percentage are supported.

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