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Scheduling on the Router Hardware, PIC, MIC, and MPC Interface Families

Table 1 compares the PIC, MIC, and MPC interface families with regard to scheduling abilities or features. Note that this table reflects the ability to perform the function at the PIC, MIC, or MPC interface level and not necessarily on the system as a whole.

In this table, the OSE PICs refer to the 10-port 10-Gigabit OSE PICs (described in some guides as the 10-Gigabit Ethernet LAN/WAN PICs with SFP+).

Table 1: Scheduling on the Router Hardware and Interface Families Compared

Scheduling Feature:

M320 and T Series

MIC and MPC Interfaces

IQ PICs

IQ2 PICs

IQ2E PICs

OSE PICs on T Series

Enhanced IQ PICs

Per–unit scheduling

–

Yes, for EQ MPC

Yes

Yes

Yes

–

Yes

Physical port and logical unit shaping

–

Yes

–

Yes

Yes

–

Yes

Guaranteed rate or peak rate support

–

Yes

–

Yes, supports both CIR and PIR on the same logical unit.

Yes

Yes, at the queue level

Yes, at the logical unit

Excess rate support

–

Yes

–

–

–

Yes

Yes, at the logical unit

Shared scheduler support

–

–

–

Yes

Yes

–

–