show ptp global-information

Displays if PTP is configured globally.

PTP domain with values from 0 through 127. The default value is 0. Only one PTP domain is supported at any given point in time.

Clock mode is either boundary or ordinary.

IEEE-2008, Enterprise, G.8275.1, G.8275.2.enh, SMPTE-ST 2059-2, AES67, and Combined AES67 and SMPTE-ST 2059-2.

Indicates whether the servo type applied on the platform is the default or the enhanced version.

Priority value of the clock: 0 through 255. The default is 128. The lower value takes precedence.

Priority value of the clock: 0 through 255. The default is 128. This value is used to differentiate and prioritize the primary clocks when the priority1-value is the same for different primary clocks in a network. The lower value takes precedence.

Method by which the announce, synchronization, and delay-response packet rates are negotiated between the primary and the client before a PTP session is established. Unicast negotiation is enabled or disabled.

Denotes whether the conversion from clock class to QL is enabled or disabled.

Denotes the user defined clock class to QL conversion.

Denotes the SNMP trap generation status (Enabled or Disabled).

Delay Request Timeout

The default value is 30 seconds. The range is from 30 to 300 seconds.

Displays if transparent clock mode is enabled or disabled.

Display the status of the transparent clock operation. The following status is as follows:

• N/A—Transparent clock is not configured.

• Active—Transparent clock is configured and working properly.

• sync-in-progress—This is a temporary state. During startup, all the PHYs are synchronized with each other. This status also occurs when a new PIC is plugged in to the switch and all the PHYs go through the synchronization cycle again.

  Note:

  Transparent clock operation is disabled during the synchronization of PHYs.

• Inactive—Transparent clock is configured but not working properly. This indicates a hardware error in PHY timestamping logic.

Displays if syntonized transparent clock mode is enabled or disabled.

Displays the Passive Port Monitoring (PPM) status (Enabled or Disabled) (only on PTX10004, PTX10008 devices).

PPM delay request interval supporting G.8275.1 specifications. The default value is -4, or (only on PTX10004, PTX10008 devices).

Display the status of the syntonized transparent clock operation. The following status is as follows:

• N/A—Syntonized transparent clock is not configured.

• Active—Syntonized transparent clock is configured and working properly.

• sync-in-progress—This is a temporary state. During startup, all the PHYs are synchronized with each other. This status also occurs when a new PIC is plugged into the switch and all the PHYs go through the synchronization cycle again.

  Note:

  Syntonized transparent clock operation is disabled during the synchronization of PHYs.

• Inactive—Syntonized transparent clock is configured but not working properly. This indicates a hardware error in PHY timestamping logic.

The number of UTC leap seconds is 37 seconds by default. However, you can configure a different value.

Displays the maximum phase offset in nanoseconds that is adjusted by the G.8275.2 enhanced servo in a phase-aligned state. A higher phase adjust threshold permits a clock to tolerate phase offset changes because of higher network packet delay variation (PDV).

Displays the frequency offset in parts per billion (ppb) that the servo locks with. Locking with a higher frequency lock threshold allows a quicker frequency lock, although at the expense of a higher phase offset per window in the phase-aligned state.

Displays he maximum phase offset in nanoseconds with which G.8275.2 enhanced servo enters the phase-aligned state. Phase locking with a higher phase lock threshold leads to the servo and time receiver getting into the phase-aligned state quickly.